- Category:
- SCM
- Tags:
-
[VHDL]
[源码]
- File Size:
- 111kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- liuhguo
Description: Verilog HDL source code, the display segment digital tube digital cumulative, testing through
- [TLC549] - verilog TLC549AD sampling procedures, th
- [clock] - prepared by the clock divider verilog HD
File list (Check if you may need any files):
seg7led
.......\int_div.bsf
.......\int_div.v
.......\lpm_constant0.bsf
.......\lpm_constant0.cmp
.......\lpm_constant0.v
.......\lpm_constant0_bb.v
.......\lpm_counter0.bsf
.......\lpm_counter0.cmp
.......\lpm_counter0.v
.......\lpm_counter0_bb.v
.......\lpm_counter0_waveforms.html
.......\seg7led.asm.rpt
.......\seg7led.bdf
.......\seg7led.cdf
.......\seg7led.done
.......\seg7led.dpf
.......\seg7led.fit.rpt
.......\seg7led.fit.smsg
.......\seg7led.fit.summary
.......\seg7led.flow.rpt
.......\seg7led.map.rpt
.......\seg7led.map.smsg
.......\seg7led.map.summary
.......\seg7led.pin
.......\seg7led.pof
.......\seg7led.qpf
.......\seg7led.qsf
.......\seg7led.qws
.......\seg7led.sim.rpt
.......\seg7led.sof
.......\seg7led.sta.rpt
.......\seg7led.sta.summary
.......\seg7led.tan.rpt
.......\seg7led.tan.summary
.......\seg7led.vwf
.......\seg7led_assignment_defaults.qdf
.......\segmain.bsf
.......\segmain.v
.......\segmain.v.bak
.......\segmain.vhd.bak
.......\setup.tcl
.......\setup.tcl.bak
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