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Title: Log_Shifter_Gate_Level_Design Download
 Description: Log Shifter Gate Level Design using Verilog(IC design Lab) and Lab Note
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Log Shifter Gate Level Design
.............................\lab01_demo.pdf
.............................\lab01_ex.pdf
.............................\password.txt
.............................\source code
.............................\...........\Demo
.............................\...........\....\LAB01_EX1_ANS
.............................\...........\....\.............\LAB01_EX1_ANS.mpf
.............................\...........\....\.............\MUX16.v
.............................\...........\....\.............\MUX16_STAGE1.v
.............................\...........\....\.............\PATTERN.v
.............................\...........\....\.............\SHIFTER.v
.............................\...........\....\.............\SHIFTER.v.bak
.............................\...........\....\.............\SIGN.v
.............................\...........\....\.............\TESTBED.v
.............................\...........\....\.............\vsim.wlf
.............................\...........\....\.............\work
.............................\...........\....\.............\....\@m@u@x16
.............................\...........\....\.............\....\........\verilog.asm
.............................\...........\....\.............\....\........\_primary.dat
.............................\...........\....\.............\....\........\_primary.vhd
.............................\...........\....\.............\....\@m@u@x16_@s@t@a@g@e1
.............................\...........\....\.............\....\....................\verilog.asm
.............................\...........\....\.............\....\....................\_primary.dat
.............................\...........\....\.............\....\....................\_primary.vhd
.............................\...........\....\.............\....\@p@a@t@t@e@r@n
.............................\...........\....\.............\....\..............\verilog.asm
.............................\...........\....\.............\....\..............\_primary.dat
.............................\...........\....\.............\....\..............\_primary.vhd
.............................\...........\....\.............\....\@s@h@i@f@t@e@r
.............................\...........\....\.............\....\..............\verilog.asm
.............................\...........\....\.............\....\..............\_primary.dat
.............................\...........\....\.............\....\..............\_primary.vhd
.............................\...........\....\.............\....\@s@i@g@n
.............................\...........\....\.............\....\........\verilog.asm
.............................\...........\....\.............\....\........\_primary.dat
.............................\...........\....\.............\....\........\_primary.vhd
.............................\...........\....\.............\....\@t@e@s@t@b@e@d
.............................\...........\....\.............\....\..............\verilog.asm
.............................\...........\....\.............\....\..............\_primary.dat
.............................\...........\....\.............\....\..............\_primary.vhd
.............................\...........\....\.............\....\_info
.............................\...........\ex1
.............................\...........\...\fulladd.v
.............................\...........\...\fulladd.v.bak
.............................\...........\...\fulladd4.v
.............................\...........\...\halfadd.v
.............................\...........\...\halfadd.v.bak
.............................\...........\...\mux2_to_1.v
.............................\...........\...\mux2_to_1.v.bak
.............................\...........\...\mux4_to_1.v
.............................\...........\...\mux4_to_1.v.bak
.............................\...........\...\ncverilog.log
.............................\...........\...\partial_sum.v
.............................\...........\...\partial_sum.v.bak
.............................\...........\...\PATTERN.v
.............................\....

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