Multiple Numbers Calculator
...........................\DEMO
...........................\....\MNC.v
...........................\....\PATTERN.v
...........................\....\TESTBED.v
...........................\EX
...........................\..\booth.v
...........................\..\booth.v.bak
...........................\..\CSA.v
...........................\..\CSA.v.bak
...........................\..\FA.v
...........................\..\ncverilog.log
...........................\..\ripple_adder27.v
...........................\..\ripple_adder27.v.bak
...........................\..\syn.tcl
...........................\..\TEST_2.v
...........................\..\TEST_2.v.bak
...........................\..\TRIANGLE.mpf
...........................\..\TRIANGLE.v
...........................\..\TRIANGLE.v.bak
...........................\..\TRIANGLE_SYN.sdf
...........................\..\TRIANGLE_SYN.v
...........................\..\umc18_neg.v
...........................\..\vsim.wlf
...........................\..\wallace_tree.v
...........................\..\wallace_tree.v.bak
...........................\..\work
...........................\..\....\@c@s@a
...........................\..\....\......\verilog.asm
...........................\..\....\......\_primary.dat
...........................\..\....\......\_primary.vhd
...........................\..\....\@f@a
...........................\..\....\....\verilog.asm
...........................\..\....\....\_primary.dat
...........................\..\....\....\_primary.vhd
...........................\..\....\@t@e@s@t_2
...........................\..\....\..........\verilog.asm
...........................\..\....\..........\_primary.dat
...........................\..\....\..........\_primary.vhd
...........................\..\....\@t@r@i@a@n@g@l@e
...........................\..\....\................\verilog.asm
...........................\..\....\................\_primary.dat
...........................\..\....\................\_primary.vhd
...........................\..\....\booth
...........................\..\....\.....\verilog.asm
...........................\..\....\.....\_primary.dat
...........................\..\....\.....\_primary.vhd
...........................\..\....\ripple_adder27
...........................\..\....\..............\verilog.asm
...........................\..\....\..............\_primary.dat
...........................\..\....\..............\_primary.vhd
...........................\..\....\wallace_tree
...........................\..\....\............\verilog.asm
...........................\..\....\............\_primary.dat
...........................\..\....\............\_primary.vhd
...........................\..\....\_info
...........................\Introduction_to_MUL_Design.pdf
...........................\Lab02_demo
...........................\..........\Lab02_demo
...........................\..........\..........\area_out.txt
...........................\..........\..........\a_in.txt
...........................\..........\..........\b_in.txt
...........................\..........\..........\c_in.txt
...........................\..........\..........\PATTERN.v
...........................\..........\..........\SYN
...........................\..........\..........\...\area_out.txt
...........................\..........\..........\...\a_in.txt
...........................\..........\..........\...\b_in.txt
...........................\..........\..........\...\c_in.txt
...........................\..........\..........\...\PATTERN.v
...........................\..........\..........\...\run.f
...........................\..........\..........\...\run_dc
...........................\..........\..........\...\syn.tcl
...........................\..........\..........\...\TESTBED.v
...........................\..........\..........\...\umc18_neg.v
...........................\..........\..........\TESTBED.v
...........................\..........\..........\TESTBED.v.bak
...........................\lab02_demo.pdf
...........................\lab02_ex.pdf
...................