Description: Based systemcc c++ As a modeling language, on-chip-chip bus masters, from the equipment, arbiter, and bus modeling itself. Given from the device memory, including fast, slow memory, and universal serial main equipment including direct-type main equipment, obstruction-type equipment, non-blocking-type main equipment in addition to its own bus and bus arbiter.
To Search:
- [IP_parse] - IP packet interception, analysis, traffi
- [arbiter] - VHDL source code sharing, sharing of res
File list (Check if you may need any files):
6_on_chip_bus
.............\arbiter.cpp
.............\arbiter.h
.............\arbiter_if.h
.............\blocking_if.h
.............\bus.cpp
.............\bus.h
.............\direct_if.h
.............\display_tools.h
.............\fast_mem.h
.............\main.cpp
.............\master_blocking.cpp
.............\master_blocking.h
.............\master_direct.cpp
.............\master_direct.h
.............\master_non_blocking.cpp
.............\master_non_blocking.h
.............\non_blocking_if.h
.............\on_chip_bus.dsp
.............\on_chip_bus.dsw
.............\on_chip_bus.ncb
.............\on_chip_bus.opt
.............\on_chip_bus.plg
.............\request.h
.............\slave_if.h
.............\slow_mem.h
.............\test.h
.............\tools.cpp
.............\types.cpp
.............\types.h
.............\uart.h
.............\uart_logic.h
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