Description: The use of Verilog language, top-down hierarchical management design idea Verilog HDL description of the behavior and structure of a description of the realization of frequency meter 8, 4 0 detection circuit principle of the amendment note
- [source3-6] - Verilog HDL 135 cases Guide : Verilog HD
- [veriloghdlQuickStart.Zip] - Verilog HDL Quick Start, which contains
- [fcout] - Cymometer source code, good performance,
- [Freq] - Simple digital frequency meter, using Ve
- [dianzishejidasai] - 2003 National Design Competition Electro
- [dispdecoder] - written in Verilog Digital Cymometer dis
- [freq_meter] - Frequency meter Verilog implementation f
File list (Check if you may need any files):
fre_ctrl.v
给定4个0的修正.ppt
频率计count10.v
频率计latch_16.v
Download