Description: Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
- [H16550_2[1].0V] - specialized processor and peripheral int
- [sarm9beta] - arm9 core framework to achieve a simple,
- [cpu] - RISC cpu, using Verilog prepared and det
- [ARelativelySimpleRISCCPU] - A Relatively Simple RISC CPU design sour
- [16bit_cpu] - 16 of RISC_CPU, everyone should have to
- [verilog_risc] - RISC state machine consists of three fun
- [16cpu] - To achieve 16-bit design of the contents
- [processor.tar] - i need of vhdl code for 32-bit risc proc
- [risc32] - VHDL design and simulation of the 32-bit
File list (Check if you may need any files):
embedded_risc
.............\Machine_Language
.............\................\program.txt
.............\SOC_Design.pdf
.............\Test_Bench_Verilog
.............\..................\Top_level_tb.tf
.............\Verilog
.............\.......\ACC.V
.............\.......\ALU.V
.............\.......\bus_arbiter.v
.............\.......\cmd_ack.v
.............\.......\cmd_decoder.v
.............\.......\cmd_detector.v
.............\.......\cmd_generator.v
.............\.......\cmd_internal_reg.v
.............\.......\command_if.v
.............\.......\CONTROL.V
.............\.......\data_cache_way0.v
.............\.......\data_cache_way1.v
.............\.......\data_cache_way2.v
.............\.......\data_cache_way3.v
.............\.......\data_in_reg.v
.............\.......\data_port.v
.............\.......\dma_cntrl.v
.............\.......\dma_fifo.v
.............\.......\dma_internal_reg.v
.............\.......\flash_ctrl.v
.............\.......\fsm.v
.............\.......\instruction_cache_way0.v
.............\.......\instruction_cache_way1.v
.............\.......\instruction_cache_way2.v
.............\.......\instruction_cache_way3.v
.............\.......\IR.V
.............\.......\k9f1g08u0m.v
.............\.......\lru_data_cache.v
.............\.......\lru_instruction_cache.v
.............\.......\MEM.V
.............\.......\MUX12.V
.............\.......\MUX16.V
.............\.......\oe_generator.v
.............\.......\parameter.v
.............\.......\PC.V
.............\.......\ras_cas_delay.v
.............\.......\ref_ack.v
.............\.......\ref_timer.v
.............\.......\risc.v
.............\.......\sdram.v
.............\.......\sdramctrl_rtl.v
.............\.......\sdram_cntrl.v
.............\.......\sdram_mux.v
.............\.......\sdram_port.v
.............\.......\soc.v
.............\.......\timer.v
.............\.......\transcript
.............\.......\uart.v
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