Description: sdram control procedures, process control port is divided into modules, clock modules, data transfer module and refresh modules
File list (Check if you may need any files):
sdram_vhdl_lattice
..................\LIB.DLS
..................\rd1007.pdf
..................\sd_cnfg.acf
..................\sd_cnfg.fit
..................\sd_cnfg.hif
..................\sd_cnfg.jam
..................\sd_cnfg.jbc
..................\sd_cnfg.mmf
..................\sd_cnfg.ndb
..................\sd_cnfg.pin
..................\sd_cnfg.pof
..................\sd_cnfg.rpt
..................\sd_cnfg.snf
..................\SD_CNFG.sym
..................\Sd_cnfg.vhd
..................\sd_rfrsh.acf
..................\sd_rfrsh.fit
..................\sd_rfrsh.hif
..................\sd_rfrsh.jam
..................\sd_rfrsh.jbc
..................\sd_rfrsh.mmf
..................\sd_rfrsh.ndb
..................\sd_rfrsh.pin
..................\sd_rfrsh.pof
..................\sd_rfrsh.rpt
..................\sd_rfrsh.snf
..................\SD_RFRSH.sym
..................\Sd_rfrsh.vhd
..................\sd_sig.acf
..................\sd_sig.hif
..................\Sd_sig.vhd
..................\sd_state.acf
..................\sd_state.fit
..................\sd_state.hif
..................\sd_state.jam
..................\sd_state.jbc
..................\sd_state.mmf
..................\sd_state.ndb
..................\sd_state.pin
..................\sd_state.pof
..................\sd_state.rpt
..................\sd_state.snf
..................\SD_STATE.sym
..................\Sd_state.vhd
..................\sd_top.acf
..................\sd_top.hif
..................\Sd_top.vhd
..................\U0750024.DLS
..................\U3831423.DLS
..................\U5442055.DLS
..................\U5492444.DLS
..................\U5679513.DLS
..................\U6435128.DLS
..................\U7025646.DLS
..................\U9146771.DLS
..................\U9392154.DLS
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