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Title: jishu60 Download
 Description: verilog example verilog modules were used to design a way of timer 60S.
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File list (Check if you may need any files):
jishu60
.......\block1.bsf
.......\block1.v
.......\db
.......\..\jishu60.asm.qmsg
.......\..\jishu60.cbx.xml
.......\..\jishu60.cmp.cdb
.......\..\jishu60.cmp.hdb
.......\..\jishu60.cmp.logdb
.......\..\jishu60.cmp.rdb
.......\..\jishu60.cmp.tdb
.......\..\jishu60.cmp0.ddb
.......\..\jishu60.dbp
.......\..\jishu60.db_info
.......\..\jishu60.eco.cdb
.......\..\jishu60.eds_overflow
.......\..\jishu60.fit.qmsg
.......\..\jishu60.hier_info
.......\..\jishu60.hif
.......\..\jishu60.map.cdb
.......\..\jishu60.map.hdb
.......\..\jishu60.map.logdb
.......\..\jishu60.map.qmsg
.......\..\jishu60.pre_map.cdb
.......\..\jishu60.pre_map.hdb
.......\..\jishu60.psp
.......\..\jishu60.rtlv.hdb
.......\..\jishu60.rtlv_sg.cdb
.......\..\jishu60.rtlv_sg_swap.cdb
.......\..\jishu60.sgdiff.cdb
.......\..\jishu60.sgdiff.hdb
.......\..\jishu60.sim.hdb
.......\..\jishu60.sim.qmsg
.......\..\jishu60.sim.rdb
.......\..\jishu60.sim.vwf
.......\..\jishu60.sld_design_entry.sci
.......\..\jishu60.sld_design_entry_dsc.sci
.......\..\jishu60.syn_hier_info
.......\..\jishu60.tan.qmsg
.......\..\wed.zsf
.......\Dec7s.bsf
.......\Dec7s.v
.......\jishi.bsf
.......\jishi.v
.......\jishu60.asm.rpt
.......\jishu60.done
.......\jishu60.fit.rpt
.......\jishu60.fit.summary
.......\jishu60.flow.rpt
.......\jishu60.map.rpt
.......\jishu60.map.summary
.......\jishu60.pin
.......\jishu60.pof
.......\jishu60.qpf
.......\jishu60.qsf
.......\jishu60.qws
.......\jishu60.sim.rpt
.......\jishu60.tan.rpt
.......\jishu60.tan.summary
.......\jishu60.v
.......\jishu60.vwf
    

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