Description: This sourse is modified and I have added the program of FIFO,so its function is better then privious one.I hope it is helpful for you!
- [AD] - FPGA control module of the AD7321 is per
- [2] - This paper introduces a high-accuracy AD
- [AD7864] - AD7864 control logic. Verilog language.
File list (Check if you may need any files):
AD7864
......\AD7864.asm.rpt
......\AD7864.done
......\AD7864.fit.rpt
......\AD7864.fit.smsg
......\AD7864.fit.summary
......\AD7864.flow.rpt
......\AD7864.map.rpt
......\AD7864.map.smsg
......\AD7864.map.summary
......\AD7864.pin
......\AD7864.pof
......\AD7864.qpf
......\AD7864.qsf
......\AD7864.sim.rpt
......\AD7864.sof
......\AD7864.tan.rpt
......\AD7864.tan.summary
......\AD7864.v
......\AD7864.v.bak
......\AD7864_test1.vwf
......\Block1.bdf
......\db
......\..\AD7864.asm.qmsg
......\..\AD7864.cbx.xml
......\..\AD7864.cmp.bpm
......\..\AD7864.cmp.cdb
......\..\AD7864.cmp.ecobp
......\..\AD7864.cmp.hdb
......\..\AD7864.cmp.logdb
......\..\AD7864.cmp.rdb
......\..\AD7864.cmp.tdb
......\..\AD7864.cmp0.ddb
......\..\AD7864.cmp_bb.cdb
......\..\AD7864.cmp_bb.hdb
......\..\AD7864.cmp_bb.logdb
......\..\AD7864.cmp_bb.rcf
......\..\AD7864.dbp
......\..\AD7864.db_info
......\..\AD7864.eco.cdb
......\..\AD7864.eds_overflow
......\..\AD7864.fit.qmsg
......\..\AD7864.hier_info
......\..\AD7864.hif
......\..\AD7864.map.bpm
......\..\AD7864.map.cdb
......\..\AD7864.map.ecobp
......\..\AD7864.map.hdb
......\..\AD7864.map.logdb
......\..\AD7864.map.qmsg
......\..\AD7864.map_bb.cdb
......\..\AD7864.map_bb.hdb
......\..\AD7864.map_bb.logdb
......\..\AD7864.pre_map.cdb
......\..\AD7864.pre_map.hdb
......\..\AD7864.psp
......\..\AD7864.pss
......\..\AD7864.rpp.qmsg
......\..\AD7864.rtlv.hdb
......\..\AD7864.rtlv_sg.cdb
......\..\AD7864.rtlv_sg_swap.cdb
......\..\AD7864.sgate.rvd
......\..\AD7864.sgate_sm.rvd
......\..\AD7864.sgdiff.cdb
......\..\AD7864.sgdiff.hdb
......\..\AD7864.signalprobe.cdb
......\..\AD7864.sim.cvwf
......\..\AD7864.sim.hdb
......\..\AD7864.sim.qmsg
......\..\AD7864.sim.rdb
......\..\AD7864.sld_design_entry.sci
......\..\AD7864.sld_design_entry_dsc.sci
......\..\AD7864.smp_dump.txt
......\..\AD7864.syn_hier_info
......\..\AD7864.tan.qmsg
......\..\AD7864.tis_db_list.ddb
......\..\prev_cmp_AD7864.asm.qmsg
......\..\prev_cmp_AD7864.fit.qmsg
......\..\prev_cmp_AD7864.map.qmsg
......\..\prev_cmp_AD7864.qmsg
......\..\prev_cmp_AD7864.sim.qmsg
......\..\prev_cmp_AD7864.tan.qmsg
......\..\wed.wsf
......\FIFO_Buffer.v
......\FIFO_Buffer.v.bak
......\lpm_fifo0.bsf
......\lpm_fifo0.v
......\lpm_fifo0_bb.v
......\lpm_fifo0_inst.v
......\lpm_fifo0_syn.bsf
......\lpm_fifo0_syn.v
......\lpm_fifo0_syn.v.bak
......\lpm_fifo0_waveforms.html
......\test.v
......\test.v.bak