Description: 2dpsk, maxplus software, including schematic connection \ each module code can be run has been pin package, can be directly downloaded to FPGA chip
- [2DPSK] - VHDL language used to achieve digital tr
- [psktodpsk] - psk to DPSK conversion (absolute phase s
- [dpsk] - DPSK describes the entire process, inclu
- [cpsk_dpsk] - Phase shift keying digital communication
File list (Check if you may need any files):
2psk_final
..........\2psk_fangzhen.acf
..........\2psk_fangzhen.gdf
..........\2psk_fangzhen.hif
..........\2psk_final.acf
..........\2psk_final.gdf
..........\2psk_final.hif
..........\2psk_final.sym
..........\2psk_tiaozhi.acf
..........\2psk_tiaozhi.fit
..........\2psk_tiaozhi.gdf
..........\2psk_tiaozhi.hex
..........\2psk_tiaozhi.hif
..........\2psk_tiaozhi.mmf
..........\2psk_tiaozhi.ndb
..........\2psk_tiaozhi.pin
..........\2psk_tiaozhi.pof
..........\2psk_tiaozhi.rpt
..........\2psk_tiaozhi.snf
..........\2psk_tiaozhi.sof
..........\2psk_tiaozhi.ttf
..........\2psk_top.acf
..........\2psk_top.gdf
..........\2psk_top.hif
..........\code.sym
..........\code.v
..........\delayy.gdf
..........\delayy.sym
..........\div1024.sym
..........\div1024.v
..........\div32.acf
..........\div32.hif
..........\div32.sym
..........\div32.v
..........\div64.sym
..........\div64.v
..........\dpll.sym
..........\dpll.v
..........\f1_zb.acf
..........\f1_zb.hif
..........\f1_zb.sym
..........\f1_zb.v
..........\f2_zb.acf
..........\f2_zb.hif
..........\f2_zb.sym
..........\f2_zb.v
..........\LIB.DLS
..........\lpf.sym
..........\lpf.v
..........\m5.acf
..........\m5.hif
..........\m5.sym
..........\m5.v
..........\mult.gdf
..........\mult.sym
..........\mux.acf
..........\mux.hif
..........\mux.sym
..........\mux.v
..........\mx7821.sym
..........\mx7821.v
..........\pj.sym
..........\pj.v
..........\rom16_1.acf
..........\rom16_1.hif
..........\rom16_1.v
..........\rom16_2.v
..........\sin16.mif
..........\sin_16.acf
..........\sin_16.hif
..........\sin_16.mif
..........\subdelay.acf
..........\subdelay.hif
..........\subdelay.sym
..........\subdelay.v
..........\U0452698.DLS
..........\U1189921.DLS
..........\U1824807.DLS
..........\U4622607.DLS
..........\U5977041.DLS
..........\U6106634.DLS
..........\U7537125.DLS
..........\U8132588.DLS
..........\U9254269.DLS
..........\wf_zk.acf
..........\wf_zk.hif
..........\wf_zk.sym
..........\wf_zk.v
..........\zx.acf
..........\zx.hif
..........\zx.sym
..........\zx.v
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