Description: FPGA-based signal acquisition and spectral analysis, prepared with VHDL, Quartus compression bag is the next project. AD sampling state machine used to achieve, and deposited LPM_RAM. The design of a UART module (state machine is realized), the data can be sent to the PC machine.
- [ram] - primitive code using VHDL prepared RAM,
- [EmbeddedprogrammeinLinux] - linux learning classical information, a
- [50vvoltmeter] - Through an external keyboard to the syst
- [AD] - For AD conversion, is very good for you
- [FFT_VHDL] - fft is a fundamental signal processing a
- [TLC549] - verilog TLC549AD sampling procedures, th
- [yinpinxinhaofenxiyi] - VHDL-based audio signal analyzer, an ele
- [CCD] - CCD digital camera the entire code, DMA
- [EP1C3_12_5_RSV] - FPGA-based digital storage oscilloscope,
- [ad574] - vhdl prepared, completed ad control chip
File list (Check if you may need any files):
EP1C3_12_7_SPCTR
................\ADSRAM.VHD
................\ADSUART.ACF
................\ADSUART.asm.rpt
................\ADSUART.CDF
................\ADSUART.done
................\ADSUART.fit.summary
................\ADSUART.flow.rpt
................\ADSUART.HIF
................\ADSUART.map.summary
................\ADSUART.MMF
................\ADSUART.PIN
................\ADSUART.QPF
................\ADSUART.QSF
................\ADSUART.QWS
................\ADSUART.SOF
................\ADSUART.tan.summary
................\ADSUART.VHD
................\cmp_state.ini
................\LPMRAM.VHD
................\README
................\......\DATA.TXT
................\......\FreqAna.exe
................\......\FreqAnaM5.dll
................\......\GW48使用readme.txt
................\......\GW48使用readme1.txt
................\STP1.STP
................\SUART.VHD
................\U_BAUD.VHD
................\U_REC.VHD
................\U_XMIT.VHD
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