- Category:
- SCM
- Tags:
-
[ASM]
[源码]
- File Size:
- 2.33mb
- Update:
- 2012-11-26
- Downloads:
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- Uploaded by:
- dj_richard
Description: To achieve the development of a stopwatch with VERILOG Design, (1) be familiar with key scanning, image stabilization and digital control key driver interface circuit theory (2) master key scanning, image stabilization and digital control key driver interface circuit design and development (3) control the state machine practical applications.
File list (Check if you may need any files):
miaobiao\cnt10.v
........\cnt6.v
........\control.v
........\counter.v
........\disp.v
........\divider.v
........\divider_100.v
........\miaobiao.cr.mti
........\miaobiao.mpf
........\stopwatch.v
........\test.counter.v
........\test_divider.v
........\transcript
........\vsim.wlf
........\wlftdv0xk7
........\wlfte016va
........\wlftmmkwd1
........\wlftmy7mg2
........\wlftwr5yty
........\.ork\_info
........\....\test_divider\_primary.dat
........\....\............\_primary.vhd
........\....\.....counter\_primary.dat
........\....\............\_primary.vhd
........\....\stopwatch\_primary.dat
........\....\.........\_primary.vhd
........\....\fdivision\_primary.dat
........\....\.........\_primary.vhd
........\....\disp\verilog.asm
........\....\....\_primary.dat
........\....\....\_primary.vhd
........\....\counter\_primary.dat
........\....\.......\_primary.vhd
........\....\.....\_primary.dat
........\....\.....\_primary.vhd
........\....\..ntrol\verilog.asm
........\....\.......\_primary.dat
........\....\.......\_primary.vhd
........\....\@c@n@tl0\verilog.asm
........\....\........\_primary.dat
........\....\........\_primary.vhd
........\....\......6\_primary.dat
........\....\.......\_primary.vhd
........\....\_temp
........\....\test_divider
........\....\test_counter
........\....\stopwatch
........\....\fdivision
........\....\disp
........\....\counter
........\....\count
........\....\control
........\....\@c@n@tl0
........\....\@c@n@t6
........\work
miaobiao
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