Description: Received frequency and initial phase may be arbitrarily changed sinusoidal analog signals from 50KHz to 50MHz can provide a total of 1024 frequency points, and the frequency of the phase are arbitrary adjustable
To Search:
- [MyAssets] - C# version of Fixed Assets Management Sy
- [Csharpcy_src] - VS2005 environment, a set of interfaces
File list (Check if you may need any files):
dds vhdl\adder10b.vhd
........\adder32b.vhd
........\db\altsyncram_fdq.tdf
........\..\altsyncram_sg11.tdf
........\..\altsyncram_vf11.tdf
........\..\dds.cbx.xml
........\..\dds.cmp.rdb
........\..\dds.db_info
........\..\dds.eco.cdb
........\..\dds.hif
........\..\dds.map.hdb
........\..\dds.map.qmsg
........\..\dds.qpf
........\..\dds.sld_design_entry.sci
........\..\dds.sld_design_entry_dsc.sci
........\..\dds.tis_db_list.ddb
........\..\ddsding.cbx.xml
........\..\ddsding.cmp.rdb
........\..\ddsding.db_info
........\..\ddsding.eco.cdb
........\..\ddsding.hif
........\..\ddsding.map.hdb
........\..\ddsding.map.qmsg
........\..\ddsding.sld_design_entry.sci
........\..\ddsding.sld_design_entry_dsc.sci
........\..\ddsding.tis_db_list.ddb
........\..\hgf.cbx.xml
........\..\hgf.cmp.rdb
........\..\hgf.db_info
........\..\hgf.eco.cdb
........\..\hgf.hif
........\..\hgf.map.hdb
........\..\hgf.map.qmsg
........\..\hgf.qpf
........\..\hgf.sld_design_entry.sci
........\..\hgf.sld_design_entry_dsc.sci
........\..\hgf.tis_db_list.ddb
........\dds.asm.rpt
........\dds.done
........\dds.fit.eqn
........\dds.fit.rpt
........\dds.fit.summary
........\dds.flow.rpt
........\dds.map.eqn
........\dds.map.rpt
........\dds.map.summary
........\dds.pin
........\dds.qar
........\dds.qarlog
........\dds.qpf
........\dds.qsf
........\dds.qws
........\dds.tan.rpt
........\dds.tan.summary
........\ddsding.flow.rpt
........\ddsding.map.rpt
........\ddsding.map.summary
........\ddsding.qpf
........\ddsding.qsf
........\ddsding.qws
........\ddsding.vhd
........\ddsding_assignment_defaults.qdf
........\dds_assignment_defaults.qdf
........\....restored\adder10b.vhd
........\............\adder32b.vhd
........\............\assignment_defaults.qdf
........\............\db\altsyncram_fdq.tdf
........\............\..\dds.db_info
........\............\..\dds.eco.cdb
........\............\..\dds.sld_design_entry.sci
........\............\dds.asm.rpt
........\............\dds.cbx.xml
........\............\dds.done
........\............\dds.fit.eqn
........\............\dds.fit.rpt
........\............\dds.fit.summary
........\............\dds.flow.rpt
........\............\dds.map.eqn
........\............\dds.map.rpt
........\............\dds.map.summary
........\............\dds.pin
........\............\dds.qpf
........\............\dds.qsf
........\............\dds.qws
........\............\dds.tan.rpt
........\............\dds.tan.summary
........\............\ddsding.qws
........\............\ddsding.vhd
........\............\dds_assignment_defaults.qdf
........\............\reg10b.vhd
........\............\reg32b.vhd
........\............\sin_rom.inc
........\............\sin_rom.vhd
........\............\sin_rom_inst.vhd
........\hgf.qsf
........\hgf_assignment_defaults.qdf
........\hgf_description.txt
........\reg10b.vhd
........\reg32b.vhd
........\sin_rom.bsf
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