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- 2012-11-26
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- jungolf
Description: Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design
- [HDLC] - HDLC link layer protocol of the CRC chec
- [hdlc.tar] - HDLC interface, written using VHDL, with
- [crc16_8bit.v] - Using Verilog hardware description langu
- [hdlc_vhdl] - This a VHDL implementation of an HDLC co
- [ethernet] - : This paper presents a FPGA-based Embed
- [hdlc] - HDLC controller base on FPGA
- [hdlc] - The code of HDLC protocol.Receive and tr
- [eth_ocm_80_3] - MAC ethernet ip opencore
- [e1framerdeframer_latest] - E1 signal to achieve a framing, CRC chec
File list (Check if you may need any files):
HDLC协议的VHDL源码\hdlc\fifo_64.vhd
..................\....\hdlc_rx.vhd
..................\....\hdlc_tx.vhd
..................\....\top.vhd
..................\使用说明请参看右侧注释====〉〉.txt
..................\hdlc
HDLC协议的VHDL源码
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