Description: The oscillator frequency is 4.096 MHz, the system synchronous clock is 256KHz, and each time slot occupies 8 bits.
The number of the four branches is 8, respectively:
1, 1, 1, 0, 0, 1, 0, 1; 1, 0, 1, 1, 0, 0, 1; 1, 0, 1, 1, 1, 0, 1;
1, 1, 1, 0, 1, 0, 1, 1;
The method of multiple connection is adopted.
- library IEEE
Use the IEEE. Std_logic_1164. All
Use the IEEE. Std_logic_unsigned. All
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实验二 同步复接器的VHDL建模和设计举例.doc
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