weitongbu Digital phase-locked loop to achieve bit

Title: weitongbu

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Communication-Mobile
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File Size:
578kb
Update:
2012-11-26
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1261009749

Description: Digital phase-locked loop to achieve bit synchronization signal extraction, including schematics, and source code

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To Search: weitongbu

[gardner] - This a MATLAB environment, gardner-bit s
[tongbujishudexiangguanziliao] - Relevant information of Synchronous tech
[TONGBUTIQU] - FPGA realization of the synchronization
[mancodec] - mancodec fpga
[bit_synch] - I wrote the MSK demodulation synchroniza
[synchronization] - Various synchronization experiment and s
[Verilog_module] - Write Verilog FPGA-based phase detector
[PLLfpgapaper] - Paper digital PLL, FPGA implementation f
[weitongbu_datain] - This a good simulation of bit synchroniz
[mach_test_ok] - verilog Manchester encoding and decoding

File list (Check if you may need any files):

位同步提取\1.jpg
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..........\cpld仿真说明.wps
..........\project.rar
..........\说明文档.txt
位同步提取

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