Description: This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly used to solve most of the data related to the structure related to the water processing multiplication and division problems, and realize the network that can shield the interrupt.
File list (Check if you may need any files):
CPU source code\ALU 组件\Booth乘法器\BoothMul.v
...............\........\并行无符号乘法器\Multiple.v
...............\........\无符号除法器\div.v
...............\........\超前进位加法器32位\CarryLookaheadAdder32.v
...............\........\..............64位\CarryLookaheadAdder64.v
...............\........\..............8位\CarryLookaheadAdder8.v
...............\单周期\ADDER.bsf
...............\......\ADDER.v
...............\......\ALU.bsf
...............\......\ALU.v
...............\......\CalPC.v
...............\......\CPU.bdf
...............\......\CPU.qpf
...............\......\CPU.vwf
...............\......\CU.bsf
...............\......\CU.v
...............\......\data.mif
...............\......\DataMemory.bsf
...............\......\DataMemory.v
...............\......\dataram.bsf
...............\......\dataram.v
...............\......\dataram_bb.v
...............\......\EXPAND.bsf
...............\......\EXPAND.v
...............\......\inst.mif
...............\......\InstMemory.bsf
...............\......\InstMemory.v
...............\......\instrom.bsf
...............\......\instrom.v
...............\......\MUX21.bsf
...............\......\MUX21.v
...............\......\MUX51.bsf
...............\......\MUX51.v
...............\......\PCAdder.bsf
...............\......\PCAdder.v
...............\......\PCCounter.bsf
...............\......\PCCounter.v
...............\......\Register.bsf
...............\......\Register.v
...............\......\SHIFT2.bsf
...............\......\SHIFT2.v
...............\......\SHIFT26.bsf
...............\......\SHIFT26.v
...............\......\target.bsf
...............\多周期\CPU.qpf
...............\......\CPU.v
...............\流水线\arith.v
...............\......\com.v
...............\......\CPU.qpf
...............\......\CPU.qsf
...............\......\CPU.qws
...............\......\CPU.v
...............\......\CPU.vwf
...............\......\data1.mif
...............\......\data2.mif
...............\......\data3.mif
...............\......\data4.mif
...............\......\.b\CPU.db_info
...............\......\..\CPU.eco.cdb
...............\......\..\CPU.sld_design_entry.sci
...............\......\inst.mif
...............\......\inst.v
...............\......\lpm_dataram1.v
...............\......\lpm_dataram2.v
...............\......\lpm_dataram3.v
...............\......\lpm_dataram4.v
...............\......\lpm_div.v
...............\......\lpm_divs.v
...............\......\lpm_InstRom.v
...............\......\lpm_mul.v
...............\......\lpm_muls.v
...............\......\lpm_pll.v
...............\ALU 组件\Booth乘法器
...............\........\并行无符号乘法器
...............\........\无符号除法器
...............\........\超前进位加法器32位
...............\........\超前进位加法器64位
...............\........\超前进位加法器8位
...............\流水线\db
...............\ALU 组件
...............\单周期
...............\多周期
...............\流水线
CPU source code
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