Description: Ultrasonic flowmeter in which the design process, this part of the control chip ACEX1K series EP1K50QC208-3 in the code, using the VHDL language, which includes LCD12864 read and write code, traffic handling
To Search:
- [ourdev] - 51 single-chip microcomputer-based ultra
- [mnncf] - Analog interpolation method, the princip
File list (Check if you may need any files):
v1.7.4-RC\DELAY5US.vhd
.........\ON_OFF.vhd
.........\SCOUNT_10.vhd
.........\SCOUNT_20.vhd
.........\counter20.vhd
.........\TEST.vwf
.........\test.qpf
.........\test.qsf
.........\counter20.bsf
.........\test.done
.........\DELAY5US.bsf
.........\divclk1MHz.vhd
.........\divclk1MHz.bsf
.........\ON_OFF.bsf
.........\SCOUNT_10.bsf
.........\SCOUNT_20.bsf
.........\test.bdf
.........\test.map.rpt
.........\test.flow.rpt
.........\test.map.summary
.........\test.pin
.........\test.fit.rpt
.........\test.fit.summary
.........\test.sof
.........\test.pof
.........\test.asm.rpt
.........\test.tan.summary
.........\test.tan.rpt
.........\test.sim.rpt
.........\VELOCITY_VOLUME.vhd
.........\FUNC_PROD.vhd
.........\velocity_volume.bsf
.........\divclk500kHz.vhd
.........\lc1_ctl.vhd
.........\divclk500kHz.bsf
.........\lc1_ctl.bsf
.........\test.qws
.........\test.cdf
.........\test.dpf
.........\Waveform1.vwf
.........\新建 文本文档 (3).txt
.........\Waveform2.vwf
.........\Waveform2.sim.vwf
.........\复件 ON_OFF.vhd
.........\locker.vhd
.........\comparator.bsf
.........\locker.bsf
.........\locker2.vhd
.........\test.sim.vwf
.........\TEST2.vwf
.........\locker2.bsf
.........\test.sim.0715.vwf
.........\db\TESTV1_1.psp
.........\..\TESTV1_1.db_info
.........\..\TESTV1_1.fit.qmsg
.........\..\TESTV1_1.rpp.qmsg
.........\..\TESTV1_1.map.qmsg
.........\..\TESTV1_1.cmp.logdb
.........\..\wed.zsf
.........\..\TESTV1_1.dbp
.........\..\TESTV1_1.cbx.xml
.........\..\TESTV1_1.hier_info
.........\..\TESTV1_1.sim.qmsg
.........\..\TESTV1_1.hif
.........\..\TESTV1_1.rtlv_sg_swap.cdb
.........\..\TESTV1_1.pre_map.cdb
.........\..\TESTV1_1.sim.hdb
.........\..\TESTV1_1.rtlv_sg.cdb
.........\..\TESTV1_1.asm.qmsg
.........\..\add_sub_2nh.tdf
.........\..\TESTV1_1.map.logdb
.........\..\add_sub_1nh.tdf
.........\..\add_sub_j8h.tdf
.........\..\add_sub_ejh.tdf
.........\..\TESTV1_1.map.cdb
.........\..\TESTV1_1.syn_hier_info
.........\..\TESTV1_1.sim.vwf
.........\..\TESTV1_1.sim.rdb
.........\..\TESTV1_1.rtlv.hdb
.........\..\TESTV1_1.tan.qmsg
.........\..\TESTV1_1.sgate.rvd
.........\..\TESTV1_1.pre_map.hdb
.........\..\TESTV1_1.map.hdb
.........\..\TESTV1_1.eco.cdb
.........\..\TESTV1_1.eds_overflow
.........\..\TESTV1_1.sgdiff.cdb
.........\..\TESTV1_1.sgdiff.hdb
.........\..\TESTV1_1.sld_design_entry_dsc.sci
.........\..\TESTV1_1.sgate_sm.rvd
.........\..\TESTV1_1.cmp.hdb
.........\..\TESTV1_1.cmp.tdb
.........\..\TESTV1_1.cmp.rdb
.........\..\TESTV1_1.cmp0.ddb
.........\..\TESTV1_1.cmp.cdb
.........\..\TESTV1_1.sld_design_entry.sci
.........\..\test.hif
.........\..\test.db_info
.........\..\test.fit.qmsg
.........\..\test.cbx.xml
.........\..\test.sim.hdb
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