DDR2deFPGAsheji Using the Virtex-4 FPGA devices to

Title: DDR2deFPGAsheji

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2012-11-26
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wdxybhb

Description: Using the Virtex-4 FPGA devices to achieve DDR SDRAM and DDR2 SDRAM controller operation timing

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To Search: FPGA SDRAM DDR2 virtex-5

[ddr_verilog_xilinx] - DDR (double data rate) SDRAM controller
[SRAM_2] - FPGA SDRAM controller source FPGA SDRAM
[HighSpeedAD] - FPGA
[DDR_SDRAM_verilog] - DDR (double rate) SDRAM controller refer
[ddrsrdram] - ddr sdram information
[FPGAbasedSDRAMControll] - FPGA-based SDRAM Controller Realization
[FPGA_DSP] - Virtex-II Pro _ Virtex-II Pro X Full Dat
[dsp-book] - High-Performance DSP Using Virtex-4 FPGA
[lcd1602] - 1602 through the FPGA to realize the liq
[DDR_SDRAM] - ddr sdram control program, lattice, and

File list (Check if you may need any files):

DDR2的FPGA设计\DDR SDRAM\DDR SDRAM\mem_interface_top.txt
..............\.........\.........\mem_interface_top_addr_gen_0.txt
..............\.........\.........\mem_interface_top_backend_fifos_0.txt
..............\.........\.........\mem_interface_top_backend_rom_0.txt
..............\.........\.........\mem_interface_top_cmp_rd_data_0.txt
..............\.........\.........\mem_interface_top_controller_iobs_0.txt
..............\.........\.........\mem_interface_top_data_gen_16.txt
..............\.........\.........\mem_interface_top_data_path_0.txt
..............\.........\.........\mem_interface_top_data_path_iobs_0.txt
..............\.........\.........\mem_interface_top_data_tap_inc.txt
..............\.........\.........\mem_interface_top_data_write_0.txt
..............\.........\.........\mem_interface_top_ddr_controller_0.txt
..............\.........\.........\mem_interface_top_idelay_ctrl.txt
..............\.........\.........\mem_interface_top_infrastructure.txt
..............\.........\.........\mem_interface_top_infrastructure_iobs_0.txt
..............\.........\.........\mem_interface_top_iobs_0.txt
..............\.........\.........\mem_interface_top_main_0.txt
..............\.........\.........\mem_interface_top_parameters_0.txt
..............\.........\.........\mem_interface_top_pattern_compare8.txt
..............\.........\.........\mem_interface_top_RAM_D_0.txt
..............\.........\.........\mem_interface_top_rd_data_0.txt
..............\.........\.........\mem_interface_top_rd_data_fifo_0.txt
..............\.........\.........\mem_interface_top_rd_wr_addr_fifo_0.txt
..............\.........\.........\mem_interface_top_tap_ctrl_0.txt
..............\.........\.........\mem_interface_top_tap_logic_0.txt
..............\.........\.........\mem_interface_top_test_bench_0.txt
..............\.........\.........\mem_interface_top_top_0.txt
..............\.........\.........\mem_interface_top_user_interface_0.txt
..............\.........\.........\mem_interface_top_v4_dm_iob.txt
..............\.........\.........\mem_interface_top_v4_dqs_iob.txt
..............\.........\.........\mem_interface_top_v4_dq_iob.txt
..............\.........\.........\mem_interface_top_wr_data_fifo_16.txt
..............\.........\.........\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf
..............\DDR2 SDRAM操作时序.pdf
..............\基于Spartan-3A的DDR2接口数据采集.doc
..............\DDR SDRAM\DDR SDRAM
..............\DDR SDRAM
DDR2的FPGA设计

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