uart 源码 (Verilog)\tester.v
...................\clock_divider.v
...................\control_operation.v
...................\cpu_interface.v
...................\serial_interface.v
...................\status_registers.v
...................\address_decode.v
...................\uart_tb.v
...................\uart_top.v
...................\xmit_rcv_control.v
uart 源码 (Verilog)