Description: Designed a double-precision floating-point multiplier. The device uses an improved algorithm for BOO TH generate part of the plot, with a mixed array and a tree structure to achieve the sum of the partial product, while also using a fast rounding algorithm to improve the performance of multipliers. The design of the multiplier is divided into four lines, carried out a simulation using FPGA verification result is correct and FPGA timing to achieve the results analyzed.
- [multiply] - This is my verilog hdl language used to
- [multiply2] - 18bit multipliers used booth2 the booth
- [mul(FLP)] - A 32-bit floating-point multipliers, can
- [Multiplier] - VHDL language used to describe a few exa
- [multiplier] - Multipliers in the FPGA code in VHDL Tut
- [fpu_latest[1].tar] - fpu!!!!!
- [fourkindmultiply] - Given the design of several common multi
- [VHDL] - A gate level implementation of a Booth E
- [eda] - Design using vhdl fir filter, a complete
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一种快速的浮点恩结构.pdf
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