Description: The problem to design a digital storage oscilloscope, to Xilinx, 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, internal trigger, A/D converter, D/A conversion and I/O modules) the use of VHDL language programming, arbitrary waveform one-shot, continuous playback is triggered, and storage, in accordance with the requirements of the vertical sensitivity and sweep speed of the gear set. Signal acquisition, it will be the external input signal conditioning by the signal conditioning modules to the A/D circuit input range, after A/D converted into the FPGA s internal dual-port RAM for high-speed cache, and the results through the D/A converter to give general oscilloscope shows completed, the low-frequency signals in real-time sampling and high-frequency signals equivalent sampling and data storage playback. Been tested, the system as a whole indices are good, the vertical sensitivity and scan speed indicators meet
- [OssilloscopeAlgorithm] - This e-book for a detailed description o
- [ARM_GRAPHIC] - In the arm on the analog-to-digital osci
- [ADC] - Verilog Programming with FPGA-based data
- [DigitalStorageOscilloscope] - This paper describes how to use AVR Sing
- [DSO] - Introduced the program to achieve high-s
- [FPGAAD] - FPGA control AD procedure
- [EP1C3_12_5_RSV] - FPGA-based digital storage oscilloscope,
- [AVRoscilloscope] - virtual oscilloscope avr m16 simple, sim
- [diansai] - C title in 2007 the award-winning articl
- [EDA] - The equivalent sampling technique based
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2007年数字示波器设计一等奖作品.doc
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