Description: Application of nuclear altera do the latest example of the use fft, fft nuclear follow avalon bus. Who want to use the IP core of friends altera help
- [Matlabfftsourcecode.Rar] - matlabfft
- [2C35F672_FFT] - In the Altera chip 2C35F672 platform FFT
- [FFT-IP] - FPGA based on the realization of the FFT
- [FFT-IP] - In the FPGA to achieve the fft, there is
- [FFT_verilog] - verilog implementation FFT transform, th
- [nr_divider] - This is a simple vhdl code that perform
- [GSM1] - GSM-based Intelligent Home Alarm System
- [yy] - XILINX board provided the use inside the
- [GraduationThesis] - 37 SCM practical and interesting Graduat
- [fftip] - Outstanding Master' s thesis 2008-200
File list (Check if you may need any files):
fftsoft\220model.v
.......\220model.v.bak
.......\altera\_info
.......\......_lib\_info
.......\altera_mf.v
.......\exponent_output_ver.txt
.......\fftfix16.cr.mti
.......\fftfix16.v
.......\fftfix16.v.bak
.......\fftfix16.vo
.......\fftfix16.vo.bak
.......\fftfix16_1n256cos.hex
.......\fftfix16_1n256sin.hex
.......\fftfix16_1n256sin.ver
.......\fftfix16_2n256cos.hex
.......\fftfix16_2n256sin.hex
.......\fftfix16_3n256cos.hex
.......\fftfix16_3n256sin.hex
.......\fftfix16_bb.v
.......\fftfix16_tb.v
.......\fftfix16_tb.v.bak
.......\fftifft.v
.......\fftifft.v.bak
.......\fftsoft.cr.mti
.......\fftsoftd.cr.mti
.......\fftsoftd.mpf
.......\imag_input.txt
.......\imag_output_ver.txt
.......\real_input.txt
.......\real_output_ver.txt
.......\sgate.v
.......\transcript
.......\vsim.wlf
.......\work\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
.......\....\..........................................\_primary.dat
.......\....\..........................................\_primary.vhd
.......\....\..............m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\verilog.asm
.......\....\...............................................\_primary.dat
.......\....\...............................................\_primary.vhd
.......\....\...................m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\verilog.asm
.......\....\...........................................................\_primary.dat
.......\....\...........................................................\_primary.vhd
.......\....\.l@p@m_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
.......\....\....................................\_primary.dat
.......\....\....................................\_primary.vhd
.......\....\........h@i@n@t_@e@v@a@l@u@a@t@i@o@n\verilog.asm
.......\....\....................................\_primary.dat
.......\....\....................................\_primary.vhd
.......\....\........m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\verilog.asm
.......\....\................................................\_primary.dat
.......\....\................................................\_primary.vhd
.......\....\.m@f_cycloneiii_pll\verilog.asm
.......\....\...................\_primary.dat
.......\....\...................\_primary.vhd
.......\....\.....pll_reg\verilog.asm
.......\....\............\_primary.dat
.......\....\............\_primary.vhd
.......\....\.....ram7x20_syn\verilog.asm
.......\....\................\_primary.dat
.......\....\................\_primary.vhd
.......\....\.....stratixiii_pll\verilog.asm
.......\....\...................\_primary.dat
.......\....\...................\_primary.vhd
.......\....\.............._pll\verilog.asm
.......\....\..................\_primary.dat
.......\....\..................\_primary.vhd
.......\....\............_pll\verilog.asm
.......\....\................\_primary.dat
.......\....\................\_primary.vhd
.......\....\alt3pram\verilog.asm
.......\....\........\_primary.dat
.......\....\........\_primary.vhd
.......\....\...accumulate\verilog.asm
.......\....\.............\_primary.dat
.......\....\.............\_primary.vhd
.......\....\...cam\verilog.asm
.......\....\......\_primary.dat
.......\....\......\_primary.vhd
.......\....\....dr_rx\verilog.asm
.......\....\.........\_primary.dat
.......\....\.........\_primary.vhd
.......\....\.......tx\verilog.asm
.......\....\.........\_primary.dat
.......\....\.........\_primary.vhd
.......\....\....lklock\verilog.asm
.......\....\..........\_primary.dat
.......\....\..........\_primary.vhd
.......\....\...ddio_bidir\verilog.asm
.......\....\.............\_primary.dat
.......\....\.............\_primary.vhd
.......\....\........in\verilog.asm
.......\....\..........\_primary.dat
.......\....\..........\_primary.vhd
.......\....\........out\verilog.asm
.......\....\...........\_primary.dat
.......\....\...........\_primary.vhd
.......\....\....pram\verilog.asm
.......\....\........\_primary.dat
.......\....\........\_primary.vhd
.......\....\....q_dqs\verilog.asm
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