Description: This is a xinlinx Beijing in 2009 a few examples of e-competition, with some representation of embedded development is to learn a good helper.
To Search:
- [jinshai_AD] - 2006 National Design Competition Electro
- [Code] - lierda MCU s2e21 Serial to Ethernet modu
- [EZLink_Si4432_SourceCode] - Wireless FSK SI4432 communications code.
- [fashe] - ISE artillery launchers under the origin
- [Oscilloscope] - The design is designed partly in VHDL, p
File list (Check if you may need any files):
KCPSM3
......\Assembler
......\.........\int_test.psm
......\.........\KCPSM3.EXE
......\.........\ROM_form.coe
......\.........\ROM_form.v
......\.........\ROM_form.vhd
......\.........\uclock.psm
......\Docs
......\....\KCPSM3_Manual.pdf
......\....\UART_Manual.pdf
......\....\UART_real_time_clock.pdf
......\....\ug129.pdf
......\kcpsm3.ngc
......\read_me.txt
......\Verilog
......\.......\bbfifo_16x8.v
......\.......\embedded_kcpsm3.v
......\.......\kcpsm3.v
......\.......\kcpsm3_int_test.v
......\.......\kcuart_rx.v
......\.......\kcuart_tx.v
......\.......\testbench.v
......\.......\uart_clock.v
......\.......\uart_rx.v
......\.......\uart_tx.v
......\VHDL
......\....\bbfifo_16x8.vhd
......\....\embedded_kcpsm3.vhd
......\....\kcpsm3.vhd
......\....\kcpsm3_int_test.vhd
......\....\kcuart_rx.vhd
......\....\kcuart_tx.vhd
......\....\test_bench.vhd
......\....\uart_clock.vhd
......\....\uart_rx.vhd
......\....\uart_tx.vhd
labsolutions
............\VHDL
............\....\lab1
............\....\....\Assembler
............\....\....\.........\CONSTANT.TXT
............\....\....\.........\INT_TEST.COE
............\....\....\.........\INT_TEST.DEC
............\....\....\.........\INT_TEST.FMT
............\....\....\.........\INT_TEST.HEX
............\....\....\.........\INT_TEST.LOG
............\....\....\.........\INT_TEST.M
............\....\....\.........\int_test.psm
............\....\....\.........\INT_TEST.V
............\....\....\.........\INT_TEST.VHD
............\....\....\.........\KCPSM3.EXE
............\....\....\.........\LABELS.TXT
............\....\....\.........\PASS1.DAT
............\....\....\.........\PASS2.DAT
............\....\....\.........\PASS3.DAT
............\....\....\.........\PASS4.DAT
............\....\....\.........\PASS5.DAT
............\....\....\.........\ROM_form.coe
............\....\....\.........\ROM_form.v
............\....\....\.........\ROM_form.vhd
............\....\....\.........\uclock.psm
............\....\....\Flow_Lab
............\....\....\........\Flow_Lab
............\....\....\........\........\1.jhd
............\....\....\........\........\1.sch
............\....\....\........\........\1.schlog
............\....\....\........\........\Flow_Lab.ise
............\....\....\........\........\Flow_Lab.ntrc_log
............\....\....\........\........\Flow_Lab.restore
............\....\....\........\........\Flow_Lab_xdb
............\....\....\........\........\............\cst.xbcd
............\....\....\........\........\............\tmp
............\....\....\........\........\............\...\ise
............\....\....\........\........\............\...\...\version
............\....\....\........\........\............\...\...\__OBJSTORE__
............\....\....\........\........\............\...\...\............\Autonym
............\....\....\........\........\............\...\...\............\common
............\....\....\........\........\............\...\...\............\HierarchicalDesign
............\....\....\........\........\............\...\...\............\..................\HDProject
............\....\....\........\........\............\...\...\............\..................\.........\HDProject
............\....\....\........\........\............\...\...\............\..................\.........\HDProject_StrTbl
............\....\....\........\........\............\...\...\............\..................\__stored_object_table__
............\....\....\........\........\............\...\...\............\ISimPlugin
............\....\....\........\........\............\...\...\............\..........\SignalOrdering1
............\....\....\........\........\............\...\...\............\..........\...............\testbench_isim_beh.exe
............\....\....\........\........\............\...\...\............\..........\...............\testbench_isim_beh.exe_StrTbl
............\....\....\........\........\............\...\...\............\PnAutoRun
............\....\....\........\........\............\...\...\............\.........\Scripts
............\....\....\
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