Description: OR1200 minimum system, including soft-core processor OR1200, memory, bus, GPIO and UART of the RTL implementation. In SOPC2000 hardware platform. Software development environment for Ubuntu, PC, to achieve SOPC2000 and simple serial communication.
- [or1200] - or1200 core as well as some references,
- [mini_or1200] - openrisc mini_or1200, including or1200,
- [OR1200] - Using verilog written cpu, a bit more di
- [or1200_wb_ram_gpio_pll] - Quartus ii project, the hardware platfor
File list (Check if you may need any files):
or1200_wb_ram_gpio_pll_uart\gpio\tags\asyst_2\rtl\verilog\gpio_defines.v
...........................\....\....\.......\...\.......\gpio_top.v
...........................\....\....\......3\rtl\verilog\gpio_defines.v
...........................\....\....\.......\...\.......\gpio_top.v
...........................\....\....\rel_1\bench\verilog\clkrst.v
...........................\....\....\.....\.....\.......\gpio_mon.v
...........................\....\....\.....\.....\.......\tb_defines.v
...........................\....\....\.....\.....\.......\tb_tasks.v
...........................\....\....\.....\.....\.......\tb_top.v
...........................\....\....\.....\.....\.......\timescale.v
...........................\....\....\.....\.....\.......\wb_master.v
...........................\....\....\.....\doc\gpio_spec.pdf
...........................\....\....\.....\...\src\gpio_spec.doc
...........................\....\....\.....\rtl\verilog\gpio_defines.v
...........................\....\....\.....\...\.......\gpio_top.v
...........................\....\....\.....\sim\rtl_sim\bin\sim.sh
...........................\....\....\.....\.yn\bin\cons_art_umc18.inc
...........................\....\....\.....\...\...\cons_vs_umc18.inc
...........................\....\....\.....\...\...\read_design.inc
...........................\....\....\.....\...\...\reports.inc
...........................\....\....\.....\...\...\save_design.inc
...........................\....\....\.....\...\...\select_tech.inc
...........................\....\....\.....\...\...\set_env.inc
...........................\....\....\.....\...\...\tech_art_umc18.inc
...........................\....\....\.....\...\...\tech_vs_umc18.inc
...........................\....\....\.....\...\...\top_gpio.scr
...........................\....\....\.....\...\run\dodesign
...........................\....\....\.....0\bench\verilog\clkrst.v
...........................\....\....\......\.....\.......\gpio_mon.v
...........................\....\....\......\.....\.......\gpio_testbench.v
...........................\....\....\......\.....\.......\tb_defines.v
...........................\....\....\......\.....\.......\tb_tasks.v
...........................\....\....\......\.....\.......\timescale.v
...........................\....\....\......\.....\.......\wb_master.v
...........................\....\....\......\doc\gpio_spec.pdf
...........................\....\....\......\...\src\gpio_spec.doc
...........................\....\....\......\rtl\verilog\gpio_defines.v
...........................\....\....\......\...\.......\gpio_top.v
...........................\....\....\......\sim\rtl_sim\bin\cds.lib
...........................\....\....\......\...\.......\...\hdl.var
...........................\....\....\......\...\.......\...\INCA_libs\worklib\inca.linux.138.pak
...........................\....\....\......\...\.......\...\rtl_file_list
...........................\....\....\......\...\.......\...\sim.sh
...........................\....\....\......\...\.......\...\sim_file_list
...........................\....\....\......\...\.......\log\ncelab.log
...........................\....\....\......\...\.......\...\ncsim.log
...........................\....\....\......\...\.......\...\ncvlog.log
...........................\....\....\......\...\.......\run\ncelab.args
...........................\....\....\......\...\.......\...\ncsim.args
...........................\....\....\......\...\.......\...\ncsim.tcl
...........................\....\....\......\...\.......\...\ncvlog.args
...........................\....\....\......\...\.......\...\run_sim
...........................\....\....\......\.yn\bin\cons_art_umc18.inc
...........................\....\....\......\...\...\cons_vs_umc18.inc
...........................\....\....\......\...\...\read_design.inc
...........................\....\....\......\...\...\reports.inc
...........................\....\....\......\...\...\save_design.inc
...........................\....\....\......\...\...\select_tech.inc
...........................\....\....\......\.
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