Title:
DCC-_based-_ARM-JTAG-debugger
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Description: This paper describes the deletion based on DCC and JTAG debugger hardware simulation research and design process. The addition of hardware emulation download debugger, breakpoints, single step, continuous operation, read and write memory region and the basic debugging features such as register operations, there by enabling DCC channel for fast read and write memory on the target machine function. Because the process of read-write memory is the most common debugging functions, thus greatly improving the efficiency of debugging. In this paper, the first embedded system development and embedded debugger, a comprehensive introduction. Then embedded debugging in the current most widely used in JTAG JTAG technology and delete the principle introduced in detail. Then delete the on-chip debugging of the principle in-depth analysis. Finally, dig into the details of the L bdaICE the design, implementation and testing process.
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于DCC和JTAG的ARM硬件仿真调试器的研究与实现.pdf
