Title:
Design-of-LDPC-codes-on-FPGA
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Description: Design and Implementation of Parallel Architectures
Decoder for（3,6）LDPC Codes Based on FPGA
code rate of 1/2 and block length of 1008 bits has been implemented based on FPGA(StatixⅡ-EP2S30F484C3)
of Altera
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File list (Check if you may need any files):
| Filename | Size | Date |
|---|
| 基于FPGA 的（3 | 6）LDPC 码并行译码器设计与实现.pdf |
