Description: Altera' s DE2 board DM9000A network FPGA interface and its driver driver program source code, as well as the Demo program source code
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File list (Check if you may need any files):
ADDEE2_NETl\DE2_NET\.metadata\.lock
...........\.......\.........\.plugins\org.eclipse.core.resources\.projects\hello_led_0\.markers
...........\.......\.........\........\..........................\.........\...........\.properties
...........\.......\.........\........\..........................\.........\..........._syslib\.markers
...........\.......\.........\........\..........................\.........\..................\.properties
...........\.......\.........\........\..........................\.........\Nios II Device Drivers\.location
...........\.......\.........\........\..........................\.........\......................\.properties
...........\.......\.........\........\..........................\.root\108.tree
...........\.......\.........\........\..........................\.safetable\org.eclipse.core.resources
...........\.......\.........\........\..................untime\.settings\org.eclipse.cdt.core.prefs
...........\.......\.........\........\........................\.........\org.eclipse.cdt.debug.core.prefs
...........\.......\.........\........\........................\.........\org.eclipse.cdt.ui.prefs
...........\.......\.........\........\........................\.........\org.eclipse.ui.prefs
...........\.......\.........\........\............ui.workbench\dialog_settings.xml
...........\.......\.........\........\........................\workbench.xml
...........\.......\.........\version.ini
...........\.......\.sopc_builder\install.ptf
...........\.......\bht_ram.mif
...........\.......\button_pio.v
...........\.......\cmp_state.ini
...........\.......\cpu_0.ocp
...........\.......\cpu_0.v
...........\.......\cpu_0_jtag_debug_module.v
...........\.......\cpu_0_jtag_debug_module_wrapper.v
...........\.......\cpu_0_mult_cell.v
...........\.......\cpu_0_ociram_default_contents.mif
...........\.......\cpu_0_test_bench.v
...........\.......\dc_tag_ram.mif
...........\.......\DE2_NET.pof
...........\.......\DE2_NET.qpf
...........\.......\DE2_NET.qsf
...........\.......\DE2_NET.sof
...........\.......\DE2_NET.v
...........\.......\DM9000A.v
...........\.......\DM9000A_IF.v
...........\.......\epcs_controller.v
...........\.......\epcs_controller_boot_rom.hex
...........\.......\hello_led_0\.cdtbuild
...........\.......\...........\.cdtproject
...........\.......\...........\.project
...........\.......\...........\application.stf
...........\.......\...........\basic_io.h
...........\.......\...........\DM9000A.C
...........\.......\...........\DM9000A.H
...........\.......\...........\hello_led.c
...........\.......\...........\LCD.c
...........\.......\...........\LCD.h
...........\.......\...........\nios2-gdb-server.exe.stackdump
...........\.......\...........\Open_I2C.c
...........\.......\...........\Open_I2C.h
...........\.......\...........\readme.txt
...........\.......\...........\Test.c
...........\.......\...........\Test.h
...........\.......\..........._syslib\.cdtbuild
...........\.......\..................\.cdtproject
...........\.......\..................\.project
...........\.......\..................\readme.txt
...........\.......\..................\system.stf
...........\.......\I2C_0.v
...........\.......\i2c_master_bit_ctrl.v
...........\.......\i2c_master_byte_ctrl.v
...........\.......\i2c_master_defines.v
...........\.......\i2c_master_top.v
...........\.......\ic_tag_ram.mif
...........\.......\ISP1362.v
...........\.......\ISP1362_IF.v
...........\.......\jtag_uart_0.v
...........\.......\lcd_16207_0.v
...........\.......\lcd_ctrl_pio.v
...........\.......\lcd_data_pio.v
...........\.......\lcd_pio.v
...........\.......\led_green.v
...........\.......\led_pio.v
...........\.......\led_red.v
...........\.......\nios_0.ptf
...........\.......\nios_0.v
...........\.......\nios_0_generation_script
...........\.......\onchip_memory_0.hex
...........\.......\README.txt
...........\.......\Reset_Delay.v
...........\.......\rf_ram_a.mif
...........\.......\rf_ram_b.mif
...........\.......\sdram_0.v
...........\.......\sdram_0_test_component.v
...........\.......\SDRA