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Title: UART_FPGA_Code Download
 Description: UART FPGA implementation process documentation, and VERILOG HDL code, hoping to help people in need, thank you
 Downloaders recently: [More information of uploader shenshunxiao]
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FilenameSizeDate
UART的FPGA实现过程-附完整的FPGAModelSimMCU代码和工程以及实现文档\fpga\V0p10\src\divider.v
...................................................................\....\.....\...\ebi.v
...................................................................\....\.....\...\rxd.v
...................................................................\....\.....\...\top.v
...................................................................\....\.....\...\txd.v
...................................................................\....\.....\...\uart.v
...................................................................\....\.....\testbench\cycloneII_v\_info
...................................................................\....\.....\.........\ModelSim.jpg
...................................................................\....\.....\.........\tcl_stacktrace.txt
...................................................................\....\.....\.........\top_tb.v
...................................................................\....\.....\.........\transcript
...................................................................\....\.....\.........\uart.cr.mti
...................................................................\....\.....\.........\uart.mpf
...................................................................\....\.....\.........\vish_stacktrace.vstf
...................................................................\....\.....\.........\vsim.wlf
...................................................................\....\.....\.........\vsim_stacktrace.vstf
...................................................................\....\.....\.........\work\divider\verilog.asm
...................................................................\....\.....\.........\....\.......\_primary.dat
...................................................................\....\.....\.........\....\.......\_primary.vhd
...................................................................\....\.....\.........\....\....sion\verilog.asm
...................................................................\....\.....\.........\....\........\_primary.dat
...................................................................\....\.....\.........\....\........\_primary.vhd
...................................................................\....\.....\.........\....\ebi\verilog.asm
...................................................................\....\.....\.........\....\...\_primary.dat
...................................................................\....\.....\.........\....\...\_primary.vhd
...................................................................\....\.....\.........\....\rxd\verilog.asm
...................................................................\....\.....\.........\....\...\_primary.dat
...................................................................\....\.....\.........\....\...\_primary.vhd
...................................................................\....\.....\.........\....\top\verilog.asm
...................................................................\....\.....\.........\....\...\_primary.dat
...................................................................\....\.....\.........\....\...\_primary.vhd
...................................................................\....\.....\.........\....\..._tb\verilog.asm
...................................................................\....\.....\.........\....\......\_primary.dat
...................................................................\....\.....\.........\....\......\_primary.vhd
...................................................................\....\.....\.........\....\.xd\verilog.asm
...................................................................\....\.....\.........\....\...\_primary.dat
...................................................................\....\.....\.........\....\...\_primary.vhd
...................................................................\....\.....\.........\....\uart\verilog.asm
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