Description: FPGA-based control ASIC CPU system design, all made with VERILOG code writing, arithmetic operations can be done
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File list (Check if you may need any files):
CPU\PIC16C57用户手册.pdf
...\RISC8 CPU 结构 (risc8).gif
...\RISC8 CPU 说明书.html
...\TB\alu.v
...\..\basic.asm
...\..\BASIC.HEX
...\..\basic.rom
...\..\CPU.cr.mti
...\..\CPU.mpf
...\..\cpu.v
...\..\dds.asm
...\..\DDS.HEX
...\..\dds.rom
...\..\dram.v
...\..\exp.v
...\..\hex2v.c
...\..\idec.v
...\..\pram.v
...\..\regs.v
...\..\risc8.vcd
...\..\runit
...\..\sindata.c
...\..\sindata.hex
...\..\tcl_stacktrace.txt
...\..\test.v
...\..\test.v.bak
...\..\test.v~
...\..\vsim.wlf
...\..\work\alu\verilog.asm
...\..\....\...\_primary.dat
...\..\....\...\_primary.vhd
...\..\....\cpu\verilog.asm
...\..\....\...\_primary.dat
...\..\....\...\_primary.vhd
...\..\....\dram\verilog.asm
...\..\....\....\_primary.dat
...\..\....\....\_primary.vhd
...\..\....\exp\verilog.asm
...\..\....\...\_primary.dat
...\..\....\...\_primary.vhd
...\..\....\idec\verilog.asm
...\..\....\....\_primary.dat
...\..\....\....\_primary.vhd
...\..\....\pram\verilog.asm
...\..\....\....\_primary.dat
...\..\....\....\_primary.vhd
...\..\....\regs\verilog.asm
...\..\....\....\_primary.dat
...\..\....\....\_primary.vhd
...\..\....\test\verilog.asm
...\..\....\....\_primary.dat
...\..\....\....\_primary.vhd
...\..\....\_info
...\..\....\alu
...\..\....\cpu
...\..\....\dram
...\..\....\exp
...\..\....\idec
...\..\....\pram
...\..\....\regs
...\..\....\test
...\..\work
...\TB
CPU
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