Description: A 32-bit pipelined processor 5. In the framework of this processor architecture is based on the MIPS instruction process for each pipeline segment, function, and in dealing with a variety of related reference to have on hand when a GCC_MIPS C language compiler, and therefore supports MIPS 1 instruction. Compiler support to make this core has practical value, the core can be applied to a variety of embedded system design, instead of the conventional single-chip system on a chip, you can also add multiple cores in a single chip and flexible bus connection to multi-processing
To Search:
File list (Check if you may need any files):
核心代码\RF_components.v
........\RF_stage.v
........\mem_module.v
........\ulit.v
........\EXEC_stage.v
........\forward.v
........\mips_core.v
........\decode_pipe.v
........\mips789_defs.v
........\ctl_fsm.v
论文\论文正文.pdf
....\封面以及摘要.pdf
核心代码
论文
Download