CLA_32.v
CLA_8.v
CLA_8.v.bak
full_adder.v
full_adder.v.bak
half.v
pg.v
tb_CLA_32.v
tb_CLA_32.v.bak
vsim.wlf
work\_info
....\_vmake
....\@c@l@a_32\verilog.psm
....\.........\_primary.dat
....\.........\_primary.dbs
....\.........\_primary.vhd
....\.......8\verilog.psm
....\........\_primary.dat
....\........\_primary.dbs
....\........\_primary.vhd
....\full_adder\verilog.psm
....\..........\_primary.dat
....\..........\_primary.dbs
....\..........\_primary.vhd
....\half\verilog.psm
....\....\_primary.dat
....\....\_primary.dbs
....\....\_primary.vhd
....\pg\verilog.psm
....\..\_primary.dat
....\..\_primary.dbs
....\..\_primary.vhd
....\tb_@c@l@a_32\verilog.psm
....\............\_primary.dat
....\............\_primary.dbs
....\............\_primary.vhd
....\_temp\vlog78hcvn
....\.....\vloghrv4rc
....\.....\vlogq0fyvn
....\.....\vlogsrdfqz