- Category:
- MPI
- Tags:
-
[VHDL]
[源码]
- File Size:
- 868kb
- Update:
- 2013-04-24
- Downloads:
- 0 Times
- Uploaded by:
- 章泽良
Description: Based on the ProASIC3 StartKit development board, describes the 8-bit address latch chip 74LS259 and the UART receiving module, to control development board led by these two modules.
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File list (Check if you may need any files):
SX\designer\impl1\designer.log
..\........\.....\designer_genhdl.log
..\........\.....\ls259.adb
..\........\.....\......dtf\verify.log
..\........\.....\ls259.ide_des
..\........\.....\ls259.pdb
..\........\.....\ls259.pdb.depends
..\........\.....\ls259.tcl
..\........\.....\ls259_ba.sdf
..\........\.....\ls259_ba.v
..\........\.....\......fp\$$FlashPro_09003.L$$
..\........\.....\........\ls259.log
..\........\.....\........\ls259.pro
..\........\.....\........\projectData\ls259.pdb
..\........\.....\sx.adb
..\........\.....\...dtf\verify.log
..\........\.....\sx.ide_des
..\........\.....\sx.pdb
..\........\.....\sx.pdb.depends
..\........\.....\sx.tcl
..\........\.....\sx_1.adb
..\........\.....\.....dtf\verify.log
..\........\.....\sx_1.ide_des
..\........\.....\sx_1.pdb
..\........\.....\sx_1.pdb.depends
..\........\.....\sx_1_ba.sdf
..\........\.....\sx_1_ba.v
..\........\.....\.....fp\$$FlashPro_09003.L$$
..\........\.....\.......\projectData\sx_1.pdb
..\........\.....\.......\sx_1.log
..\........\.....\.......\sx_1.pro
..\........\.....\sx_ba.sdf
..\........\.....\sx_ba.v
..\........\.....\...fp\$$FlashPro_09003.L$$
..\........\.....\.....\projectData\sx.pdb
..\........\.....\.....\sx.log
..\........\.....\.....\sx.pro
..\hdl\ls259.v
..\...\rec.v
..\...\sx.v
..\simulation\modelsim.ini
..\..........\modelsim.ini.sav
..\..........\modelsim.log
..\..........\postsynth\ls259\verilog.psm
..\..........\.........\.....\_primary.dat
..\..........\.........\.....\_primary.dbs
..\..........\.........\.....\_primary.vhd
..\..........\.........\rec\verilog.psm
..\..........\.........\...\_primary.dat
..\..........\.........\...\_primary.dbs
..\..........\.........\...\_primary.vhd
..\..........\.........\sx\verilog.psm
..\..........\.........\..\_primary.dat
..\..........\.........\..\_primary.dbs
..\..........\.........\..\_primary.vhd
..\..........\.........\_info
..\..........\.resynth\ls259\verilog.psm
..\..........\........\.....\_primary.dat
..\..........\........\.....\_primary.dbs
..\..........\........\.....\_primary.vhd
..\..........\........\rec\verilog.psm
..\..........\........\...\_primary.dat
..\..........\........\...\_primary.dbs
..\..........\........\...\_primary.vhd
..\..........\........\sx\verilog.psm
..\..........\........\..\_primary.dat
..\..........\........\..\_primary.dbs
..\..........\........\..\_primary.vhd
..\..........\........\_info
..\..........\run.do
..\..........\vsim.wlf
..\..........\work\ls259\verilog.psm
..\..........\....\.....\_primary.dat
..\..........\....\.....\_primary.dbs
..\..........\....\.....\_primary.vhd
..\..........\....\rec\verilog.psm
..\..........\....\...\_primary.dat
..\..........\....\...\_primary.dbs
..\..........\....\...\_primary.vhd
..\..........\....\sx\verilog.psm
..\..........\....\..\_primary.dat
..\..........\....\..\_primary.dbs
..\..........\....\..\_primary.vhd
..\..........\....\_info
..\.martgen\smartgen.aws
..\SX.prj
..\synthesis\.recordref
..\.........\backup\ls259.srr
..\.........\......\sx.srr
..\.........\......\sx_1.srr
..\.........\ls259.areasrr
..\.........\ls259.edn
..\.........\ls259.fse
..\.........\ls259.htm
..\.........\ls259.map
..\.........\ls259.sap
..\.........\ls259.sdf
..\.........\ls259.so
..\.........\ls259.srd
..\.........\ls259.srm