dual_portram\designer\impl1\designer.log
............\........\.....\simulation\postlayout\tp_ram_top\verilog.psm
............\........\.....\..........\..........\..........\_primary.dat
............\........\.....\..........\..........\..........\_primary.dbs
............\........\.....\..........\..........\..........\_primary.vhd
............\........\.....\..........\..........\_info
............\........\.....\tp_ram_top.adb
............\........\.....\...........dtf\verify.log
............\........\.....\tp_ram_top.ide_des
............\........\.....\tp_ram_top.pdb
............\........\.....\tp_ram_top.pdb.depends
............\........\.....\tp_ram_top.tcl
............\........\.....\tp_ram_top_ba.sdf
............\........\.....\tp_ram_top_ba.v
............\........\.....\...........fp\$$FlashPro_09003.L$$
............\........\.....\.............\projectData\tp_ram_top.pdb
............\........\.....\.............\tp_ram_top.log
............\........\.....\.............\tp_ram_top.pro
............\dual_portram.prj
............\hdl\ctrl_RAM.v
............\...\rec.v
............\...\send.v
............\...\tp_ram_top.v
............\simulation\dual_port_ram_R0C0.mem
............\..........\dual_port_ram_R0C1.mem
............\..........\dual_port_ram_R0C2.mem
............\..........\dual_port_ram_R0C3.mem
............\..........\modelsim.ini
............\..........\modelsim.ini.sav
............\..........\modelsim.log
............\..........\presynth\ctrl_@r@a@m\verilog.psm
............\..........\........\...........\_primary.dat
............\..........\........\...........\_primary.dbs
............\..........\........\...........\_primary.vhd
............\..........\........\dual_port_ram\verilog.psm
............\..........\........\.............\_primary.dat
............\..........\........\.............\_primary.dbs
............\..........\........\.............\_primary.vhd
............\..........\........\rec\verilog.psm
............\..........\........\...\_primary.dat
............\..........\........\...\_primary.dbs
............\..........\........\...\_primary.vhd
............\..........\........\send\verilog.psm
............\..........\........\....\_primary.dat
............\..........\........\....\_primary.dbs
............\..........\........\....\_primary.vhd
............\..........\........\tp_ram_top\verilog.psm
............\..........\........\..........\_primary.dat
............\..........\........\..........\_primary.dbs
............\..........\........\..........\_primary.vhd
............\..........\........\_info
............\..........\run.do
............\..........\vsim.wlf
............\.martgen\dual_port_ram\dual_port_ram.cxf
............\........\.............\dual_port_ram.gen
............\........\.............\dual_port_ram.log
............\........\.............\dual_port_ram.shx
............\........\.............\dual_port_ram.v
............\........\.............\dual_port_ram_R0C0.mem
............\........\.............\dual_port_ram_R0C1.mem
............\........\.............\dual_port_ram_R0C2.mem
............\........\.............\dual_port_ram_R0C3.mem
............\........\dual_port_ram_work.ixf
............\........\smartgen.aws
............\.ynthesis\.recordref
............\.........\backup\tp_ram_top.srr
............\.........\run_options.txt
............\.........\stdout.log
............\.........\.yntmp\sap.log
............\.........\......\tp_ram_top.msg
............\.........\......\tp_ram_top.plg
............\.........\......\tp_ram_top_flink.htm
............\.........\......\tp_ram_top_srr.htm
............\.........\......\tp_ram_top_toc.htm
............\.........\tp_ram_top.areasrr
............\.........\tp_ram_top.edn
............\.........\tp_ram_top.fse
............\.........\tp_ram_top.htm
............\.........\tp_ram_top.map
............\.........\tp_ram_top.sap
............\.........\tp_ram_top.sdf
............\.........\tp_ram_top.so
............\.........\tp_ram_top.srd
............\.........\tp_ram_top.srm
............\.........\tp_ram_top.srr
.........