- Category:
- Com Port
- Tags:
-
[VHDL]
[源码]
- File Size:
- 3kb
- Update:
- 2013-11-13
- Downloads:
- 0 Times
- Uploaded by:
- 三木
Description: Using Verilog realize a simple serial communication, through functional simulation and on-board debugging, had no problems receiving and sending module
To Search:
File list (Check if you may need any files):
Uart\async_receiver.v
....\async_transmitter.v
....\uart_control.v
Uart
Download