Description: Preliminary master the use of ModelSim understand TestBench preparation, Verilog HDL level design methods/parameters, parameter passing methods.
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File list (Check if you may need any files):
lab1\acc\acc.v
....\...\acc_sim.cr.mti
....\...\acc_sim.mpf
....\...\acc_tb.v
....\...\dffr.v
....\...\full_adder.v
....\...\transcript
....\...\vsim.wlf
....\...\wave.do
....\...\.ork\acc\verilog.asm
....\...\....\...\_primary.dat
....\...\....\...\_primary.vhd
....\...\....\..._tb\verilog.asm
....\...\....\......\_primary.dat
....\...\....\......\_primary.vhd
....\...\....\dffr\verilog.asm
....\...\....\....\_primary.dat
....\...\....\....\_primary.vhd
....\...\....\full_adder\verilog.asm
....\...\....\..........\_primary.dat
....\...\....\..........\_primary.vhd
....\...\....\_info
....\...\....\acc
....\...\....\acc_tb
....\...\....\dffr
....\...\....\full_adder
....\...\work
....\acc
lab1
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