Description: The design is based digital frequency synthesizer technology, using a sine lookup table to achieve waveform generation. Direct digital frequency synthesis (DDS) is an advanced circuit structure can fully digital output signal frequency under precise and fast control, DDS technology also solve the incremental output signal frequency selection signal having a very good application, DDS generated by high frequency resolution, frequency switching speed, phase-continuous frequency switching time, low phase noise output and can generate arbitrary waveforms, and many other advantages . This paper introduces the basic principles of the DDS, DDS MS for its bulk inhibition were analyzed. Programming using ultra high-speed hardware description language VHDL description DDS, on the basis of the design of the sine wave, triangle wave, square wave signal generator. Completed part of debugging software and hardware design, and the experimental prototype.
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DDS
...\control.v
...\counter.v
...\counter.v.bak
...\db
...\..\altsyncram_1191.tdf
...\..\altsyncram_fs81.tdf
...\..\DSS.ae.hdb
...\..\DSS.amm.cdb
...\..\DSS.asm.qmsg
...\..\DSS.asm.rdb
...\..\DSS.asm_labs.ddb
...\..\DSS.cbx.xml
...\..\DSS.cmp.bpm
...\..\DSS.cmp.cdb
...\..\DSS.cmp.hdb
...\..\DSS.cmp.kpt
...\..\DSS.cmp.logdb
...\..\DSS.cmp.rdb
...\..\DSS.cmp0.ddb
...\..\DSS.cmp1.ddb
...\..\DSS.cmp_merge.kpt
...\..\DSS.db_info
...\..\DSS.eda.qmsg
...\..\DSS.fit.qmsg
...\..\DSS.hier_info
...\..\DSS.hif
...\..\DSS.idb.cdb
...\..\DSS.lpc.html
...\..\DSS.lpc.rdb
...\..\DSS.lpc.txt
...\..\DSS.map.bpm
...\..\DSS.map.cdb
...\..\DSS.map.hdb
...\..\DSS.map.kpt
...\..\DSS.map.logdb
...\..\DSS.map.qmsg
...\..\DSS.map.rdb
...\..\DSS.map_bb.cdb
...\..\DSS.map_bb.hdb
...\..\DSS.map_bb.logdb
...\..\DSS.pre_map.cdb
...\..\DSS.pre_map.hdb
...\..\DSS.root_partition.map.reg_db.cdb
...\..\DSS.routing.rdb
...\..\DSS.rtlv.hdb
...\..\DSS.rtlv_sg.cdb
...\..\DSS.rtlv_sg_swap.cdb
...\..\DSS.sgdiff.cdb
...\..\DSS.sgdiff.hdb
...\..\DSS.sim.cvwf
...\..\DSS.sld_design_entry.sci
...\..\DSS.sld_design_entry_dsc.sci
...\..\DSS.smart_action.txt
...\..\DSS.sta.qmsg
...\..\DSS.sta.rdb
...\..\DSS.syn_hier_info
...\..\DSS.tis_db_list.ddb
...\..\DSS.tmw_info
...\..\logic_util_heursitic.dat
...\..\prev_cmp_DSS.asm.qmsg
...\..\prev_cmp_DSS.eda.qmsg
...\..\prev_cmp_DSS.fit.qmsg
...\..\prev_cmp_DSS.map.qmsg
...\..\prev_cmp_DSS.qmsg
...\..\prev_cmp_DSS.tan.qmsg
...\..\wed.wsf
...\DSS.asm.rpt
...\DSS.done
...\DSS.eda.rpt
...\DSS.fit.rpt
...\DSS.fit.smsg
...\DSS.fit.summary
...\DSS.flow.rpt
...\DSS.jdi
...\DSS.map.rpt
...\DSS.map.summary
...\DSS.pin
...\DSS.pof
...\DSS.qpf
...\DSS.qsf
...\DSS.qws
...\DSS.sim.rpt
...\DSS.sof
...\DSS.sta.rpt
...\DSS.sta.summary
...\DSS.tan.rpt
...\DSS.tan.summary
...\DSS.v
...\DSS.v.bak
...\DSS.vwf
...\DSS_assignment_defaults.qdf
...\DSS_description.txt
...\DSS_nativelink_simulation.rpt
...\greybox_tmp
...\...........\cbx_args.txt
...\incremental_db
...\..............\compiled_partitions
...\..............\...................\DSS.db_info
...\..............\...................\DSS.root_partition.cmp.cdb
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