- Category:
- Project Design
- Tags:
-
[PDF]
- File Size:
- 306kb
- Update:
- 2014-07-01
- Downloads:
- 0 Times
- Uploaded by:
- wu
Description: This document describes an approach based on Xilinx Endpoint Block Plus PCIe IP Core, initiated by the board of DMA Design. The design utilizes a common LocalLink interface, easy to support Xilinx PCIe hardcore compatible devices, such as Virtex 5, Virtex 6, Spartan 6, and actually ML555 ML605 development board and the actual test. In addition, the board of control of the driver package, and provides user-level read and write a simple interface to facilitate the development of the top programs.
To Search:
File list (Check if you may need any files):
Xilinx_PCIe_Core DMA.pdf
Download