- Category:
- Com Port
- Tags:
-
[VHDL]
[源码]
- File Size:
- 3kb
- Update:
- 2014-07-09
- Downloads:
- 0 Times
- Uploaded by:
- 黎静宏
Description: UART in fpga,include translate module,receive module an clock module.
To Search:
File list (Check if you may need any files):
uart\clkdiv.v
....\testuart.v
....\uartrx.v
....\uarttx.v
uart
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