- Category:
- Com Port
- Tags:
-
- File Size:
- 541kb
- Update:
- 2014-07-23
- Downloads:
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- Uploaded by:
- Zou Xingyu
Description: Based on the FPGA design, Verilog language into a, SPI universal interface module, the top has been packaged into a FIFO interface similar to that of the standard provide simulation files simulator for modelsim10.0c, waveform observation debussy.
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sim\.th_04.v.swo
...\.th_04.v.swp
...\modelsim.ini
...\rtl.f
...\run.bat
...\sim.do
...\test\@cpld_@switch_@top\_primary.dat
...\....\..................\_primary.dbs
...\....\..................\_primary.vhd
...\....\._opt\vopt0ib80s
...\....\.....\vopt16hsgh
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...\....\.....\_deps
...\....\.....1\vopt0jf4z6
...\....\......\vopt15s8w3
...\....\......\vopt1g4z6t
...\....\......\vopt209ydk
...\....\......\vopt2q2ds0
...\....\......\vopt39chnx
...\....\......\vopt3gdxke
...\....\......\vopt3wvmm4
...\....\......\vopt40iwv8
...\....\......\vopt4vmmjt
...\....\......\vopt50fyfy
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