Description: 16 FIFO hardware circuits using verilog implementation. File contains a combination of logic and storage logic to achieve the two methods, and the corresponding testbench test code
To Search:
File list (Check if you may need any files):
vsim.wlf
fifo.v
fifo_withreg.v
tb_fifo.v
tb_fifo_withReg.v
............@reg\verilog.asm
................\_primary.dat
................\_primary.vhd
fifo\verilog.asm
....\_primary.dat
....\_primary.vhd
...._withreg\verilog.asm
............\_primary.dat
............\_primary.vhd
tb_fifo\verilog.asm
.......\_primary.dat
.......\_primary.vhd
tb_fifo_with@reg
fifo
fifo_withreg
tb_fifo
Download