基于Xilinx FPGA的OFDM通信系统基带设计\Receiver\CFO_Correction.rar
.....................................\........\Channel_Equalizer.rar
.....................................\........\Deinterleaver.rar
.....................................\........\Descrambler.rar
.....................................\........\Frame_Detection.rar
.....................................\........\Phase_Tracking.rar
.....................................\........\QAM16_Demapping.rar
.....................................\........\Sampling_Frequency_Synchronization.rar
.....................................\........\Timing_Symcronization.rar
.....................................\........\Viterbi.rar
.....................................\Transmitter\clock_generator\clock_generator\clk_generator_summary.html
.....................................\...........\...............\...............\clock_generator.ise
.....................................\...........\...............\...............\clock_generator.ise_ISE_Backup
.....................................\...........\...............\...............\clock_generator.restore
.....................................\...........\...............\...............\clock_generator.v
.....................................\...........\...............\...............\clock_generator_summary.html
.....................................\...........\...............\...............\DCM1.xaw
.....................................\...........\CP_ADDER\bram1I.asy
.....................................\...........\........\bram1i.edn
.....................................\...........\........\bram1i.sym
.....................................\...........\........\bram1i.v
.....................................\...........\........\bram1i.veo
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.....................................\...........\........\bram1i.vho
.....................................\...........\........\bram1i.xco
.....................................\...........\........\bram1r.asy
.....................................\...........\........\bram1r.edn
.....................................\...........\........\bram1r.sym
.....................................\...........\........\bram1r.v
.....................................\...........\........\bram1r.veo
.....................................\...........\........\bram1r.vhd
.....................................\...........\........\bram1r.vho
.....................................\...........\........\bram1r.xco
.....................................\...........\........\bram2i.asy
.....................................\...........\........\bram2i.edn
.....................................\...........\........\bram2i.sym
.....................................\...........\........\bram2i.v
.....................................\...........\........\bram2i.veo
.....................................\...........\........\bram2i.vhd
.....................................\...........\........\bram2i.vho
.....................................\...........\........\bram2i.xco
.....................................\...........\........\bram2r.asy
.....................................\...........\........\bram2r.edn
.....................................\...........\........\bram2r.sym
.....................................\...........\........\bram2r.v
.....................................\...........\........\bram2r.veo
.....................................\...........\........\bram2r.vhd
.....................................\...........\........\bram2r.vho
.....................................\...........\........\bram2r.xco
.....................................\...........\........\CP_ADDER.ise
.....................................\...........\........\CP_ADDER.ise_ISE_Backup
.....................................\...........\........\CP_ADDER.restore
.....................................\...........\........\CP_adder.v
.....................................\...........\........\CP_adder_summary.html
.....................................\...........\........\templa