Description: xilinx SDK custom IP core, realize LED lighting, and lighting PWM pulse, the routine can be run directly. There is also a corresponding documentation, customized IP learning you deserve.
To Search:
File list (Check if you may need any files):
20150520LED_IP
..............\clock_generator_0.log
..............\data
..............\....\system.ucf
..............\drivers
..............\.......\led_ip_v1_00_a
..............\.......\..............\data
..............\.......\..............\....\led_ip_v2_1_0.mdd
..............\.......\..............\....\led_ip_v2_1_0.tcl
..............\.......\..............\src
..............\.......\..............\...\led_ip.c
..............\.......\..............\...\led_ip.h
..............\.......\..............\...\led_ip_selftest.c
..............\.......\..............\...\Makefile
..............\.......\pwm_v1_00_a
..............\.......\...........\data
..............\.......\...........\....\pwm_v2_1_0.mdd
..............\.......\...........\....\pwm_v2_1_0.tcl
..............\.......\...........\src
..............\.......\...........\...\Makefile
..............\.......\...........\...\pwm.c
..............\.......\...........\...\pwm.h
..............\.......\...........\...\pwm_selftest.c
..............\etc
..............\...\bitgen.ut
..............\...\download.cmd
..............\...\fast_runtime.opt
..............\...\system.filters
..............\...\system.gui
..............\hdl
..............\...\clock_generator_0_wrapper.vhd
..............\...\dlmb_cntlr_wrapper.vhd
..............\...\dlmb_wrapper.vhd
..............\...\elaborate
..............\...\.........\clock_generator_0_v4_02_a
..............\...\.........\.........................\hdl
..............\...\.........\.........................\...\vhdl
..............\...\.........\.........................\...\....\clock_generator.vhd
..............\...\.........\lmb_bram_elaborate_v1_00_a
..............\...\.........\..........................\hdl
..............\...\.........\..........................\...\vhdl
..............\...\.........\..........................\...\....\lmb_bram_elaborate.vhd
..............\...\ilmb_cntlr_wrapper.vhd
..............\...\ilmb_wrapper.vhd
..............\...\led_ip_0_wrapper.vhd
..............\...\led_wrapper.vhd
..............\...\lmb_bram_wrapper.vhd
..............\...\mb_plb_wrapper.vhd
..............\...\mdm_0_wrapper.vhd
..............\...\microblaze_0_wrapper.vhd
..............\...\proc_sys_reset_0_wrapper.vhd
..............\...\pwm_0_wrapper.vhd
..............\...\system.vhd
..............\...\system_stub.vhd
..............\implementation
..............\..............\bitgen.ut
..............\..............\cache
..............\..............\.....\cache.cat
..............\..............\.....\clock_generator_0_wrapper.ngc
..............\..............\.....\dlmb_cntlr_wrapper.ngc
..............\..............\.....\dlmb_wrapper.ngc
..............\..............\.....\ilmb_cntlr_wrapper.ngc
..............\..............\.....\ilmb_wrapper.ngc
..............\..............\.....\led_ip_0_wrapper.ngc
..............\..............\.....\led_wrapper.ngc
..............\..............\.....\lmb_bram_wrapper.ngc
..............\..............\.....\mb_plb_wrapper.ngc
..............\..............\.....\mdm_0_wrapper.ngc
..............\..............\.....\microblaze_0_wrapper.ngc
..............\..............\.....\proc_sys_reset_0_wrapper.ngc
..............\..............\.....\pwm_0_wrapper.ngc
..............\..............\clock_generator_0_wrapper
..............\..............\clock_generator_0_wrapper.blc
..............\..............\clock_generator_0_wrapper.ngc
..............\..............\clock_generator_0_wrapper.ngc_xst.xrpt
..............\..............\.........................\clock_generator_0_wrapper.ngc
..............\..............\.........................\xlnx_auto_0_xdb
..............\..............\.........................\_xmsgs
..............\..............\.........................\......\ngcbuild.xmsgs
..............\..............\clock_generator_0_wrapper_vhdl.prj
..............\..............\dlmb_cntlr_wrapper
..............\..............\dlmb_cntlr_wrapper.ngc
..............\..............\dlmb_cntlr_wrapper.ngc_xst.xrpt
..............\..............\dlmb_cntlr_wrapper_vhdl.prj
..............\.