Description: verilog prepared by the serial port to send and receive module, capable of setting the stop bit and the parity bit, and includes modelsim simulation files.
To Search:
File list (Check if you may need any files):
test_uart\my_uart_rx.v
.........\my_uart_top.v
.........\my_uart_tx.v
.........\Readme.txt
.........\speed_select.v
.........\speed_select.v.bak
.........\tb_uart.v
.........\tb_uart.v.bak
.........\test_uart.cr.mti
.........\test_uart.mpf
.........\vsim.wlf
.........\work\my_uart_rx\verilog.prw
.........\....\..........\verilog.psm
.........\....\..........\_primary.dat
.........\....\..........\_primary.dbs
.........\....\..........\_primary.vhd
.........\....\........top\verilog.prw
.........\....\...........\verilog.psm
.........\....\...........\_primary.dat
.........\....\...........\_primary.dbs
.........\....\...........\_primary.vhd
.........\....\.........x\verilog.prw
.........\....\..........\verilog.psm
.........\....\..........\_primary.dat
.........\....\..........\_primary.dbs
.........\....\..........\_primary.vhd
.........\....\speed_select\verilog.prw
.........\....\............\verilog.psm
.........\....\............\_primary.dat
.........\....\............\_primary.dbs
.........\....\............\_primary.vhd
.........\....\tb_uart\verilog.prw
.........\....\.......\verilog.psm
.........\....\.......\_primary.dat
.........\....\.......\_primary.dbs
.........\....\.......\_primary.vhd
.........\....\_info
.........\....\.temp\vlog02kg5n
.........\....\.....\vlogdhw9w9
.........\....\.....\vlogf11vkk
.........\....\.....\vlogi1mxk6
.........\....\.....\vlogwh0wzx
.........\....\_vmake
.........\....\my_uart_rx
.........\....\my_uart_top
.........\....\my_uart_tx
.........\....\speed_select
.........\....\tb_uart
.........\....\_temp
.........\work
test_uart
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