- Category:
- Other systems
- Tags:
-
- File Size:
- 8.82mb
- Update:
- 2015-09-26
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- Uploaded by:
- johu
Description: 8bit10bit encoding and decoding, SPI solution string, BAT656 accept the source code, and through USB3.0 to PC. After testing the FPGA Actel clock frequency 100M can meet the transmission rate of 320MB/s
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File list (Check if you may need any files):
USB3_a3p1000_9.1\aaa.dpz
................\component\work\aaa\aaa.cxf
................\.........\....\...\aaa.sdb
................\..nstraint\1.pdc
................\..........\data\1.pdc.ce
................\..........\....\usb3_top_32bit_pin.pdc.ce
................\..........\slaveFIFO2b_loopback_1_sdc.sdc
................\..........\usb3_top_32bit_pin.pdc
................\..........\usb3_top_32bit_pin_20140517.rar
................\designer\impl2\11111111\$$FlashPro_66705.L$$
................\........\.....\........\11111111.log
................\........\.....\........\11111111.pro
................\........\.....\........\projectData\slaveFIFO2b_loopback__all_in_1_synthesis_1.pdb
................\........\.....\designer.log
................\........\.....\fifo_money.ide_des
................\........\.....\pll_25_to_100.ide_des
................\........\.....\slaveFIFO2b_fpga_top.ide_des
................\........\.....\slavefifo2b_fpga_top_tb.ide_des
................\........\.....\slaveFIFO2b_loopback.tcl
................\........\.....\slaveFIFO2b_loopback_1.adb
................\........\.....\.......................dtf\verify.log
................\........\.....\slaveFIFO2b_loopback_1.ide_des
................\........\.....\slaveFIFO2b_loopback_1.pdb
................\........\.....\slaveFIFO2b_loopback_1.pdb.depends
................\........\.....\......................_fp\$$FlashPro_66705.L$$
................\........\.....\.........................\projectData\slaveFIFO2b_loopback_1.pdb
................\........\.....\.........................\slaveFIFO2b_loopback_1.log
................\........\.....\.........................\slaveFIFO2b_loopback_1.pro
................\........\.....\slaveFIFO2b_loopback_1_synthesis_1.adb
................\........\.....\...................................dtf\verify.log
................\........\.....\slaveFIFO2b_loopback_1_synthesis_1.ide_des
................\........\.....\slaveFIFO2b_loopback_1_synthesis_1.pdb
................\........\.....\slaveFIFO2b_loopback_1_synthesis_1.pdb.depends
................\........\.....\.................................._fp\$$FlashPro_66705.L$$
................\........\.....\.....................................\projectData\slaveFIFO2b_loopback_1_synthesis_1.pdb
................\........\.....\.....................................\slaveFIFO2b_loopback_1_synthesis_1.log
................\........\.....\.....................................\slaveFIFO2b_loopback_1_synthesis_1.pro
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis.adb
................\........\.....\.........................................dtf\verify.log
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis.ide_des
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis.pdb
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis.pdb.depends
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis_1.adb
................\........\.....\...........................................dtf\verify.log
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis_1.ide_des
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis_1.pdb
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis_1.pdb.depends
................\........\.....\.........................................._fp\$$FlashPro_66705.L$$
................\........\.....\.............................................\projectData\slaveFIFO2b_loopback__all_in_1_synthesis_1.pdb
................\........\.....\.............................................\slaveFIFO2b_loopback__all_in_1_synthesis_1.log
................\........\.....\.............................................\slaveFIFO2b_loopback__all_in_1_synthesis_1.pro
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis_2.adb
................\........\.....\...........................................dtf\verify.log
................\........\.....\slaveFIFO2b_loopback__all_in_1_synthesis_2.ide_des
................\........\.....\slav
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