- Category:
- MPI
- Tags:
-
[VHDL]
[源码]
- File Size:
- 4kb
- Update:
- 2015-01-18
- Downloads:
- 0 Times
- Uploaded by:
- DX
Description: Contains 32 multiplier design, verilog language, including booth encoding implementations, booth multiplier implementations, 3_2 compressor implementation 4_2 compressor to achieve and realize China Clarence tree, and two testbench file with the to the test.
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File list (Check if you may need any files):
multiply\_42c_l.v
........\boot_mul.v
........\bootcoder.v
........\csa.v
........\tb_bootmul.v
........\tb_mul.v
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