Description: SWP paper implements digital transceiver interface circuit design using Verilog language design, complete with QuartusⅡ9.1 debugging and functional simulation. In our design, the design method is used in sub-modules. The design process, we will first complete system architecture design, a clear function of each sub-modules. After each module functions were realized, then the union of all modules for debugging and simulation of the overall system, the final completion of the module design SWP digital transceiver interface.
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swp
...\100_11011.vwf
...\101_00101.vwf
...\110_01010.vwf
...\db
...\..\logic_util_heursitic.dat
...\..\prev_cmp_swp.asm.qmsg
...\..\prev_cmp_swp.fit.qmsg
...\..\prev_cmp_swp.map.qmsg
...\..\prev_cmp_swp.qmsg
...\..\prev_cmp_swp.sim.qmsg
...\..\prev_cmp_swp.sta.qmsg
...\..\swp.asm.qmsg
...\..\swp.asm.rdb
...\..\swp.asm_labs.ddb
...\..\swp.cbx.xml
...\..\swp.cmp.bpm
...\..\swp.cmp.cbp
...\..\swp.cmp.cdb
...\..\swp.cmp.ecobp
...\..\swp.cmp.hdb
...\..\swp.cmp.kpt
...\..\swp.cmp.logdb
...\..\swp.cmp.rdb
...\..\swp.cmp_merge.kpt
...\..\swp.cuda_io_sim_cache.31um_ff_1200mv_0c_fast.hsd
...\..\swp.cuda_io_sim_cache.31um_tt_1200mv_85c_slow.hsd
...\..\swp.db_info
...\..\swp.eco.cdb
...\..\swp.eds_overflow
...\..\swp.fit.qmsg
...\..\swp.fnsim.cdb
...\..\swp.fnsim.hdb
...\..\swp.fnsim.qmsg
...\..\swp.hier_info
...\..\swp.hif
...\..\swp.lpc.html
...\..\swp.lpc.rdb
...\..\swp.lpc.txt
...\..\swp.map.bpm
...\..\swp.map.cdb
...\..\swp.map.ecobp
...\..\swp.map.hdb
...\..\swp.map.kpt
...\..\swp.map.logdb
...\..\swp.map.qmsg
...\..\swp.map_bb.cdb
...\..\swp.map_bb.hdb
...\..\swp.map_bb.logdb
...\..\swp.pre_map.cdb
...\..\swp.pre_map.hdb
...\..\swp.rtlv.hdb
...\..\swp.rtlv_sg.cdb
...\..\swp.rtlv_sg_swap.cdb
...\..\swp.sgdiff.cdb
...\..\swp.sgdiff.hdb
...\..\swp.sim.cvwf
...\..\swp.sim.hdb
...\..\swp.sim.qmsg
...\..\swp.sim.rdb
...\..\swp.simfam
...\..\swp.sld_design_entry.sci
...\..\swp.sld_design_entry_dsc.sci
...\..\swp.smart_action.txt
...\..\swp.sta.qmsg
...\..\swp.sta.rdb
...\..\swp.sta_cmp.6_slow_1200mv_85c.tdb
...\..\swp.syn_hier_info
...\..\swp.tiscmp.fast_1200mv_0c.ddb
...\..\swp.tiscmp.slow_1200mv_0c.ddb
...\..\swp.tiscmp.slow_1200mv_85c.ddb
...\..\swp.tis_db_list.ddb
...\..\wed.wsf
...\decode.v
...\decode.v.bak
...\extract.v
...\extract.v.bak
...\fdivide10.v
...\fdivide10.v.bak
...\fdivide4.v
...\fdivide4.v.bak
...\fdivide40.v.bak
...\incode.v
...\incode.v.bak
...\incremental_db
...\..............\compiled_partitions
...\..............\...................\swp.root_partition.cmp.cdb
...\..............\...................\swp.root_partition.cmp.dfp
...\..............\...................\swp.root_partition.cmp.hdb
...\..............\...................\swp.root_partition.cmp.kpt
...\..............\...................\swp.root_partition.cmp.logdb
...\..............\...................\swp.root_partition.cmp.rcfdb
...\..............\...................\swp.root_partition.cmp.re.rcfdb
...\..............\...................\swp.root_partition.map.cdb
...\..............\...................\swp.root_partition.map.dpi
...\..............\...................\swp.root_partition.map.hdb
...\..............\...................\swp.root_partition.map.kpt
...\..............\README
...\para_to_serial.v.bak
...\para_to_serial10_1.v
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