face recogn.  in xilinx EDK\bitinit.log
...........................\clock_generator_0.log
...........................\libgen.log
...........................\platgen.log
...........................\platgen.opt
...........................\system.bsb
...........................\system.log
...........................\system.log.bak
...........................\system.make
...........................\system.mhs
...........................\system.mss
...........................\system.xmp
...........................\system_incl.make
...........................\wizlog
...........................\_impactbatch.log
...........................\blkdiagram\svg10.dtd
...........................\..........\system.css
...........................\..........\system.html
...........................\..........\system.svg
...........................\.ootloops\ppc440_0.elf
...........................\data\system.ucf
...........................\etc\bitgen.ut
...........................\...\download.cmd
...........................\...\fast_runtime.opt
...........................\...\xmd_ppc440_0.opt
...........................\hdl\clock_generator_0_wrapper.vhd
...........................\...\ddr2_sdram_wrapper.v
...........................\...\jtagppc_cntlr_0_wrapper.vhd
...........................\...\plb_v46_0_wrapper.vhd
...........................\...\ppc440_0_wrapper.vhd
...........................\...\proc_sys_reset_0_wrapper.vhd
...........................\...\rs232_uart_1_wrapper.vhd
...........................\...\sysace_compactflash_wrapper.vhd
...........................\...\system.vhd
...........................\...\system_stub.vhd
...........................\...\util_vector_logic_0_wrapper.vhd
...........................\...\xps_bram_if_cntlr_1_bram_wrapper.vhd
...........................\...\xps_bram_if_cntlr_1_wrapper.vhd
...........................\...\elaborate\xps_bram_if_cntlr_1_bram_elaborate_v1_00_a\hdl\vhdl\xps_bram_if_cntlr_1_bram_elaborate.vhd
...........................\implementation\bitgen.ut
...........................\..............\clock_generator_0_wrapper.ngc
...........................\..............\clock_generator_0_wrapper.ngc_xst.xrpt
...........................\..............\clock_generator_0_wrapper_vhdl.prj
...........................\..............\ddr2_sdram_wrapper.blc
...........................\..............\ddr2_sdram_wrapper.ngc
...........................\..............\ddr2_sdram_wrapper.ngc_xst.xrpt
...........................\..............\download.bit
...........................\..............\fpga.flw
...........................\..............\jtagppc_cntlr_0_wrapper.ngc
...........................\..............\jtagppc_cntlr_0_wrapper.ngc_xst.xrpt
...........................\..............\jtagppc_cntlr_0_wrapper_vhdl.prj
...........................\..............\netlist.lst
...........................\..............\plb_v46_0_wrapper.ngc
...........................\..............\plb_v46_0_wrapper.ngc_xst.xrpt
...........................\..............\plb_v46_0_wrapper_vhdl.prj
...........................\..............\ppc440_0_wrapper.blc
...........................\..............\ppc440_0_wrapper.ngc
...........................\..............\ppc440_0_wrapper.ngc_xst.xrpt
...........................\..............\ppc440_0_wrapper_vhdl.prj
...........................\..............\proc_sys_reset_0_wrapper.ngc
...........................\..............\proc_sys_reset_0_wrapper.ngc_xst.xrpt
...........................\..............\proc_sys_reset_0_wrapper_vhdl.prj
...........................\..............\rs232_uart_1_wrapper.blc
...........................\..............\rs232_uart_1_wrapper.ngc
...........................\..............\rs232_uart_1_wrapper.ngc_xst.xrpt
...........................\..............\rs232_uart_1_wrapper_vhdl.prj
...........................\..............\smartpreview.twr
...........................\..............\sysace_compactflash_wrapper.ngc
...........................\..............\sysace_compactflash_wrapper.ngc_xst.xrpt
..................