Title:
digital-equalizer-Verilog
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Description: Master thesis. The main contents are as follows: 1, the design principle of the equalizer 2, intersymbol interference (ISI) and equilibrium principle 3, adaptive equalization algorithm, mainly introduces the zero forcing algorithm, LMS algorithm, RLS algorithm, LMS adaptive equalizer Verilog design 5, the above algorithm matlab simulation
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数字均衡器的设计及Verilog实现_苏周.caj
