Filename
Size
Date
Halley_V2.0\ext_2.0\PCB\extract.log
Halley_V2.0\ext_2.0\PCB\extract.log
1
Halley_V2.0\ext_2.0\PCB\extract.log
2
Halley_V2.0\ext_2.0\PCB\extract.log
3
Halley_V2.0\ext_2.0\PCB\HALLEY_EXT_BOARD_V2_0_FINAL.brd
Halley_V2.0\ext_2.0\PCB\Imported HALLEY_EXT_BOARD_V2_0_FINAL.PrjPcb\HALLEY_EXT_BOARD_V2_0_FINAL.LOG
Halley_V2.0\ext_2.0\PCB\Imported HALLEY_EXT_BOARD_V2_0_FINAL.PrjPcb\HALLEY_EXT_BOARD_V2_0_FINAL.PcbDoc
Halley_V2.0\ext_2.0\PCB\Imported HALLEY_EXT_BOARD_V2_0_FINAL.PrjPcb\HALLEY_EXT_BOARD_V2_0_FINAL.PrjPcb
Halley_V2.0\ext_2.0\PCB\Imported HALLEY_EXT_BOARD_V2_0_FINAL.PrjPcb\History\HALLEY_EXT_BOARD_V2_0_FINAL.~(1).PcbDoc.Zip
Halley_V2.0\ext_2.0\PCB\Imported HALLEY_EXT_BOARD_V2_0_FINAL.PrjPcb\History\HALLEY_EXT_BOARD_V2_0_FINAL.~(1).PrjPcb.Zip
Halley_V2.0\ext_2.0\PCB\Imported HALLEY_EXT_BOARD_V2_0_FINAL.PrjPcb\History\HALLEY_EXT_BOARD_V2_0_FINAL.~(2).PcbDoc.Zip
Halley_V2.0\ext_2.0\PCB\Imported HALLEY_EXT_BOARD_V2_0_FINAL.PrjPcb\History\HALLEY_EXT_BOARD_V2_0_FINAL.~(2).PrjPcb.Zip
Halley_V2.0\ext_2.0\PCB\Imported HALLEY_EXT_BOARD_V2_0_FINAL.PrjPcb\History\HALLEY_EXT_BOARD_V2_0_FINAL.~(3).PcbDoc.Zip
Halley_V2.0\ext_2.0\PCB\interconn.iml
Halley_V2.0\ext_2.0\PCB\signoise.log
Halley_V2.0\ext_2.0\PCB\signoise.log
1
Halley_V2.0\ext_2.0\PCB\signoise.run\case1
Halley_V2.0\ext_2.0\PCB\signoise.run\case1
Halley_V2.0\ext_2.0\PCB\signoise.run\cases.cfg
Halley_V2.0\ext_2.0\PCB\signoise.run\cases.cfg
1
Halley_V2.0\ext_2.0\sch\EXTERAL_V2_0END.DSN
Halley_V2.0\ext_2.0\sch\exteral_v2_0end.opj
Halley_V2.0\ext_2.0\sch\EXTERAL_V2_0END.pdf
Halley_V2.0\ext_2.0\sch\TF_CARD.DSN
Halley_V2.0\ext_2.0\sch\tf_card.opj
Halley_V2.0\ext_2.0\sch\TF_CARD.pdf
Halley_V2.0\ext_2.0\sch\Thumbs.db
Halley_V2.0\main_2.0\PCB\allegro.jrl
Halley_V2.0\main_2.0\PCB\Allegro2Altium.bat
Halley_V2.0\main_2.0\PCB\AllegroBoardView.txt
Halley_V2.0\main_2.0\PCB\AllegroConnectivityView.txt
Halley_V2.0\main_2.0\PCB\AllegroExportViews.txt
Halley_V2.0\main_2.0\PCB\AllegroGeometryView.txt
Halley_V2.0\main_2.0\PCB\AllegroLayerView.txt
Halley_V2.0\main_2.0\PCB\AllegroNetRulesView.txt
Halley_V2.0\main_2.0\PCB\AllegroPadStackView.txt
Halley_V2.0\main_2.0\PCB\AllegroSymbolDefinitionsView.txt
Halley_V2.0\main_2.0\PCB\AllegroSymbolInstancesView.txt
Halley_V2.0\main_2.0\PCB\allegro_free_viewer.jrl
Halley_V2.0\main_2.0\PCB\embedded_layer_setup.log
Halley_V2.0\main_2.0\PCB\extract.log
Halley_V2.0\main_2.0\PCB\extract.log
1
Halley_V2.0\main_2.0\PCB\HALLEY_V2_0_Final.brd
Halley_V2.0\main_2.0\PCB\HALLEY_V2_0_Final.brd.alg
Halley_V2.0\main_2.0\PCB\HALLEY_V2_0_Final.brd.lck
Halley_V2.0\main_2.0\PCB\Imported HALLEY_V2_0_Final.brd.PrjPcb\HALLEY_V2_0_Final.brd.LOG
Halley_V2.0\main_2.0\PCB\Imported HALLEY_V2_0_Final.brd.PrjPcb\HALLEY_V2_0_Final.brd.PcbDoc
Halley_V2.0\main_2.0\PCB\Imported HALLEY_V2_0_Final.brd.PrjPcb\HALLEY_V2_0_Final.brd.PrjPcb
Halley_V2.0\main_2.0\PCB\Imported HALLEY_V2_0_Final.brd.PrjPcb\History\HALLEY_V2_0_Final.brd.~(1).PcbDoc.Zip
Halley_V2.0\main_2.0\PCB\Imported HALLEY_V2_0_Final.brd.PrjPcb\History\HALLEY_V2_0_Final.brd.~(1).PrjPcb.Zip
Halley_V2.0\main_2.0\PCB\Imported HALLEY_V2_0_Final.brd.PrjPcb\History\HALLEY_V2_0_Final.brd.~(2).PcbDoc.Zip
Halley_V2.0\main_2.0\PCB\Imported HALLEY_V2_0_Final.brd.PrjPcb\History\HALLEY_V2_0_Final.brd.~(2).PrjPcb.Zip
Halley_V2.0\main_2.0\PCB\interconn.iml
Halley_V2.0\main_2.0\PCB\signoise.log
Halley_V2.0\main_2.0\PCB\signoise.log
1
Halley_V2.0\main_2.0\PCB\signoise.run\case1
Halley_V2.0\main_2.0\PCB\signoise.run\case1
Halley_V2.0\main_2.0\PCB\signoise.run\cases.cfg
Halley_V2.0\main_2.0\PCB\signoise.run\cases.cfg
1
Halley_V2.0\main_2.0\sch\HALLEY_V2_0END.DSN
Halley_V2.0\main_2.0\sch\halley_v2_0end.opj
Halley_V2.0\main_2.0\sch\halley_v2_0end.pdf
Halley_V2.0\main_2.0\sch\HALLEY_V2_0END_0.DBK
Halley_V2.0\main_2.0\sch\Thumbs.db
Halley_V2.0\main_2.0\Thumbs.db